Semiconductor memory device having test mode

Details Semiconductor memory device having test mode Semiconductor memory device having test mode

1997-12-04

1999-11-30

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

365203, 365226, G11C 700

Patent

active

059954272

ABSTRACT:
In a DRAM, a bit-line potential inputting node of an equalizer provided for each odd-numbered pair of bit lines is provided separately from a bit-line potential inputting node of an equalizer provided for each even-numbered pair of bit lines. In burn-in testing, one node receives a high level and the other node receives a low level to simultaneously apply electric field stress between adjacent pairs of bit lines. This allows sufficient acceleration of initial failures in burn-in testing.

REFERENCES:
patent: 5544108 (1996-08-01), Thomann
patent: 5659512 (1997-08-01), Koyanagi et al.
patent: 5717652 (1998-02-01), Ooishi
patent: 5761141 (1998-06-01), Kabashi et al.
patent: 5793686 (1998-08-01), Furutani et al.
patent: 5815451 (1998-09-01), Tsuchida
"Wafer Burn-in(WBI) Technology for High Density DRAM" H.Noji et al., Technical Report of IEICE. SDM94-22, ICD94-33(1994-05), pp. 41-46.

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