Semiconductor memory device having substrate isolation of a swit

Details Semiconductor memory device having substrate isolation of a swit Semiconductor memory device having substrate isolation of a swit

1987-11-18

1990-04-03

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Capacitors

365182, 357 236, G11C 1134, G11C 1124, H01L 2978

Patent

active

049146289

ABSTRACT:
A semiconductor memory has a first insulating layer formed on one major surface of a silicon single crystal substrate having a hole portion. The hole portion is filled with a material of a first conductivity type up to the depth of the first insulating layer. A first single crystal silicon layer is formed on the first insulating layer and a diffused region of the first single crystal silicon layer is formed on the first insulating layer and on the material of a first conductivity type. Source and drain regions are formed by doping the first single crystal silicon layer with a first impurity up to high degree of concentration. A second insulating layer is then formed on the first single crystal silicon layer with a low resistive portion formed on this second insulating layer to form source and drain regions. A second single crystal silicon layer is formed along the wall surfaces of the second insulating layer and the low resistive portion. A gate insulating film is formed along wall surfaces of the second single crystal silicon layer and the diffused region on the low resistive portion and having the hole portion on the material of a first conductivity type. Finally, a gate electrode is formed by filling the hole portion of the gate insulating film with the material of a first conductivity type.

REFERENCES:
patent: 4673962 (1987-06-01), Chatterjee et al.
patent: 4717942 (1988-01-01), Nakamura et al.
patent: 4721987 (1988-01-01), Baglee et al.
patent: 4751557 (1988-06-01), Sunami et al.
patent: 4752819 (1988-06-01), Koyama
patent: 4761385 (1985-08-01), Pfiester
patent: 4786954 (1988-11-01), Morie et al.
patent: 4792834 (1988-12-01), Uchida
patent: 4794563 (1988-12-01), Maeda
ISSCC, Session XIX: Dynamic RAMs, "A 4Mb Dram with Cross Point Trench Transistor Cell", by A. H. Shah et al., Feb. 21, 1986, pp. 268-269.

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