Static information storage and retrieval – Read/write circuit – Including specified plural element logic arrangement
Reexamination Certificate
2000-09-13
2002-08-27
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including specified plural element logic arrangement
C365S063000, C365S230030
Reexamination Certificate
active
06442078
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to a semiconductor memory device having a structure suitable for a memory-combined LSI having a large internal bus width.
2. Description of the Prior Art
A memory/logic merged LSI formed by integrating a logic circuit and a memory core part operated by the logic circuit on a single semiconductor substrate is recently developed.
In such a memory/logic merged LSI, the memory core part captures a number of write data from the logic circuit through a number of I/O nodes (I/O: input/output) or transfers a number of read data to the logic circuit. Thus, a large quantity of data can be processed at a high speed.
The memory/logic merged LSI has a possibility of implementing an extremely high data transfer rate by enlarging an internal bus width (bit number of simultaneously transferred data) for transferring data between the logic circuit and the memory core part and improving the operating frequency.
When increasing the capacity of memory cells for processing a large quantity of data, however, the scale of gates selectively connecting a number of internal data buses transferring write data and read data with bit lines is disadvantageously increased.
Thus, while the operating frequency tends to improve following recent improvement of the performance of transistors, increase of the memory capacity or the scale of the gates results in delay in wires connecting elements of the memory core part. Such wiring delay degrades the operating performance of the memory core part as well as the throughput of the memory/logic merged LSI itself.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a semiconductor memory device capable of implementing a high data transfer rate by relaxing influence by wiring delay resulting from increase of the memory capacity.
The semiconductor memory device according to the present invention comprises a memory cell array including a plurality of word lines arranged in a row direction, a plurality of bit lines arranged in a column direction and a plurality of memory cells, an interface area for transmitting/receiving signals to/from an external device, and a memory operation circuit arranged between the interface area and the memory cell array for writing data received from the interface area in the memory cell array and reading data from the memory cell array to output the data to the interface area.
According to the aforementioned semiconductor memory device, therefore, a circuit group related to memory operations is arranged in the vicinity of the interface area, and hence no wire may be extended. Thus, a high data transfer rate can be implemented between the semiconductor memory device and the external device by relaxing influence exerted by wiring delay.
Preferably, the semiconductor memory device further comprises an internal data bus arranged in the row direction for transmitting write data output from the memory operation circuit to the memory cell array in a write operation and transmitting read data read from the memory cell array to the memory operation circuit in a read operation and a sense amplifier block including a plurality of sense amplifiers provided in correspondence to the plurality of bit lines for amplifying the potentials of the corresponding bit lines and a plurality of input/output gates provided in correspondence to the plurality of sense amplifiers respectively for transmitting data between the corresponding bit lines and the internal data bus.
Alternatively, the semiconductor memory device preferably further comprises an internal data bus arranged in the row direction for transmitting/receiving data to/from the memory cell array, the memory operation circuit preferably includes a selection circuit selecting a memory cell subjected to a write operation and a read operation on the basis of an address signal received from the interface area and a data input/output circuit outputting write data to the internal data bus on the basis of input data received from the interface area in the write operation and outputting output data to the interface area on the basis of read data received from the internal data bus in the read operation.
Alternatively, the semiconductor memory device preferably further comprises an internal data bus arranged in the row direction for transmitting write data output from the memory operation circuit in a write operation and transmitting read data read from the memory cell array to the memory operation circuit in a read operation and a sense amplifier block including a plurality of sense amplifiers provided in correspondence to the plurality of bit lines respectively for amplifying the potentials of the corresponding bit lines and a plurality of input/output gates provided in correspondence to the plurality of bit lines respectively for electrically connecting/disconnecting the corresponding bit lines to/from the internal data bus, and the memory operation circuit preferably includes a selection circuit selecting a memory cell subjected to the write operation and the read operation on the basis of an address signal received from the interface area and a data input/output circuit outputting the write data to the internal data bus on the basis of input data received from the interface area in the write operation and outputting output data to the interface area on the basis of the read data received from the internal data bus in the read operation.
According to the aforementioned semiconductor memory device, therefore, an address-system circuit and a preamplifier/write driver, for example, are arranged in the vicinity of the interface area, whereby no wire may be extended. Further, the internal data bus is arranged in the row direction, so that the data bus length is not influenced also when the memory cell array is increased in size in the column direction. Thus, the semiconductor memory device is particularly suitable for a memory array, having a large internal bus width, of a memory/logic merged LSI.
More preferably, the internal data bus includes a local data bus arranged on the sense amplifier block and electrically connected with a bit line corresponding to the memory cell selected by the selection circuit, a global data bus arranged in the row direction and connected with the data input/output circuit, and a connection line connecting the local data bus and the global data bus with each other. In particular, the memory cell array includes a split area arranged in the column direction and a plurality of subarrays split by the split area, and the connection line is arranged on the split area in the column direction. In particular, each of the plurality of word lines is split into a plurality of subword lines, and the split area is an area for driving a subword line corresponding to the selected memory cell. Alternatively, the split area is an area for pile-driving each of the plurality of word lines.
Therefore, the internal data bus arranged in the row direction can be implemented by layering the internal data bus.
Further, a bus connection line can be arranged through the split area (a subword driver area in the case of a split word line system or a word line pile-driving area in the case of a general word line system, for example) extending in the column direction of the memory cell array.
More preferably, the interface area includes a first interface area having an address area receiving the address signal from the external device and a second interface area having a data input/output area for receiving the input data from the external device and outputting the output data to the external device, the selection circuit is arranged between the first interface area and an end of the memory cell array, and the data input/output circuit is arranged between the second interface area and another end of the memory cell array.
Alternatively, the interface area more preferably includes a first interface area having an address area for rece
Elms Richard
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Tuan T.
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