Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1997-12-12
1999-03-30
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
711154, 36523009, G06F 1200
Patent
active
058901973
ABSTRACT:
A semiconductor memory device including a serial I/O buffer; DRAM cells; and SAM cells arranged in line, the SAM cells corresponding to the DRAM cells in one row. In the device in a first mode, the SAM cells are divided into N first portions each having boundaries, data stored in the SAM cells being transferred to the serial I/O buffer sequentially until the SAM cells in the boundaries of the first portions are transferred to the serial I/O buffer. In a second mode, the SAM cells are divided into M (N>M) second portions each having boundaries, data stored in the SAM cells being transferred to the serial I/O buffer sequentially until the SAM cells in the boundaries of the second portions arc transferred to the serial input output buffer. The semiconductor-memory device further includes a circuit for detecting changes from the first mode to the second mode and from the second mode to the first mode. The semiconductor memory device further includes a circuit for generating first and second signals. When the mode is changed from the first mode to the second mode, the circuit generates the first signal. When the mode is changed from the second mode to the first mode the circuit generates the second signal.
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Chow Christopher S.
Kabushiki Kaisha Toshiba
Swann Tod R.
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