Semiconductor memory device having spare word lines

Static information storage and retrieval – Read/write circuit – Bad bit

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36523006, G11C 700

Patent

active

059599081

ABSTRACT:
An OR circuit generates a spare word line group selection signal based on output signals of address coincidence detection circuits and the OR circuit generates an upper/low-order selection signal. A spare word line selecting signal generation circuit generates a spare word line selection signal based on the upper/low-order selection signal and common word line selection signal and a word line driving circuit substitutes the spare word line or lines in a redundancy memory cell array in the unit of lines smaller than the number of word lines constructing one word line group in the memory cell array according to the spare word line group selection signal and spare word line selection signal.

REFERENCES:
patent: 4752914 (1988-06-01), Nakano et al.
patent: 5047983 (1991-09-01), Iwai et al.
patent: 5267205 (1993-11-01), Hamada
patent: 5467457 (1995-11-01), Kohda et al.
patent: 5586075 (1996-12-01), Miwa
patent: 5703817 (1997-12-01), Shiratake et al.

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