Semiconductor memory device having signal generating circuitry f

Details Semiconductor memory device having signal generating circuitry f Semiconductor memory device having signal generating circuitry f

1997-07-16

1998-11-03

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Data refresh

36523004, 365240, 36523006, 365236, G11C 700

Patent

active

058319212

ABSTRACT:
In a DRAM, an upper address is assigned to each of ways W0 and W1, and a lower address is assigned to each word line WL in each of ways W0 and W1. A self-refresh start trigger generating circuit senses start of self-refresh, and a refresh address change sensing circuit senses change in an upper address. Based on the result of sensing, way selection signals RX0 and RX1 will not be reset and held at an active level while ways W0 and W1 are selected, respectively. Consequently, power consumption can be reduced compared to a conventional example in which signals RX0 and RX1 are reset every time a single word line WL is selected.

REFERENCES:
patent: 5568440 (1996-10-01), Tsukude et al.
"A 256M Dram with Simplified Register Control for Low Power Self Refresh and Rapid Burn-in" by Seung-Moon Yoo et al., 1994 Symposium on VLSI Circuits Digest of Technical Papers, pp. 85-86.

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