Semiconductor memory device having shortened testing time

Details Semiconductor memory device having shortened testing time Semiconductor memory device having shortened testing time

2002-03-27

2004-06-15

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Simultaneous operations

C365S200000, C365S230040, C365S230050

Reexamination Certificate

active

06751128

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device of the synchronous type including a memory cell portion which allows the data read/write to be executed.
2. Related Art
Referring to
FIG. 35
of the accompanying drawings, which is a diagram for describing a data read test in a prior art semiconductor memory device. In this figure, each of blocks A and B is made up of a memory cell portion and a sense amplifier circuit portion, respectively, wherein SDBP-A<j> and SDBP-B<j> indicate a subdata bus pair belonging to blocks A and B, respectively;
909
-A<j> and
909
-B<j> a read sense amplifier circuit portion (referred to as “RSAMP circuit portion” hereinafter) of blocks A and B; a DBP<j> data bus;
11
<j> a read amplifier circuit (referred to as “Read Amp circuit” hereinafter);
12
<j> an output buffer circuit (referred to as “Dout Buffer circuit” hereinafter); and DQ<j> a data I/O pins. In the above, the letter “j” indicates the bit of the data as read or written, and it may be one of digits 0~7 in case of the semiconductor memory device of the 8-bit configuration while being one of digits 0~15 in case of the semiconductor memory device of the 16-bit configuration. Accordingly, in case of the semiconductor memory device of the 8-bit configuration, for instance, there are provided
16
RSAMP circuit portions
909
-A<
0
>~
909
-A<
7
> and
909
-B<
0
>~
909
-B<
7
>, and 8 data bus pairs DBP<
0
>~DBP<
7
>.
In the semiconductor memory device as shown in
FIG. 35
, the data read-out in the normal mode is carried out as follows. First, the block A or B is selected according to the most significant bit (block selection bit) of the input Y-address data while the column (bit line) within the block is selected according to the other Y-address data. The row (word line) within the block is selected according to the input X-address data. The data in the memory cell defined by the selected column and row of the selected block is then read out to the data bus pairs DBP<j> by means of the RSAMP circuit portion
909
-A<j> or
909
-B<j>.
In contrast to the above, in case of the data read in the test mode (data read test), the above block selection bit is ignored by “Don't Care” operation and two data of the blocks A and B are simultaneously read out to the data bus pair DBP<J> by RSAMP circuit portions
909
-A<j> and
909
-B<j>, and then it is judged if these two data are correct or not. The test in which the address is made degenerate and two data are simultaneously read or written, is called a parallel test. In the prior art parallel test, two data are simultaneously read out by simultaneously selecting two X-addresses, which is called a degenerate X-address parallel test.
FIG. 36
is a diagram for explaining the redundant substitution of a faulty memory cell. In this FIG,
5
-A and
5
-B indicate respective memory cell portions of blocks A and B;
5
-R a redundant memory portion; CL
0
, CL
1
. . . CLm respective columns of memory cell portions
5
-A and
5
-B; RCL
0
, RCL
1
. . . columns of the redundant memory portion
5
-R; and WL
0
, WL
1
. . . WLn word lines.
In
FIG. 36
, if the memory cell defined by the column CL
0
and the word line WL
1
of the block A is faulty, the memory cells defined by columns CL
0
and CL
1
and word lines WL
0
~WLn of the block A are subject to the redundant substitution by
0
using memory cells defined by columns CL
0
~CL
1
and word lines WL
0
~WLn of the redundant memory cell portion
5
-R. Accordingly, in the redundant substitution of
FIG. 36
, if a faulty memory cell exists in Y-address=#000 when making the least significant bit of the Y-address degenerate, two Y-addresses #000 and #001 are subject to the redundant substitution.
Like this, the redundant substitution of the faulty memory cell is to redundantly replace all the memory cells belonging to the same column as the faulty memory cell, and this is called “column redundant substitution system.” As the above column redundant substitution is executed with respect to the memory cells belonging to two Y-address (two columns), it may be called “degenerate Y-address redundant substitute.”
The prior art semiconductor memory device is provided with a Y-address decode circuit including a plurality of decode circuits for decoding the Y-address data. In each of these decode circuits, the decode signals are generated based on the Y-address data from which the other one bit for the block selection bit and Y-degeneration control is deleted. With these decode signals, either two of the Y-addresses (the degenerate Y-addresses of which either one bit is made degenerate) are selected, and either one of the above two Y-addresses is selected according to the signal generated based on the above other one bit of the Y-degenerate control circuit. The reason for the redundant substitution means to takes two steps of making two Y-addresses degenerate and then carrying out the redundant substitution, is that it is judged whether or not the Y-address data as inputted is the data of the Y-address that has been subject to the redundant substitution, based on the bit of the Y-address data as inputted to the above decode circuit or based on the above decode signal.
In the above prior art semiconductor memory device, however, there has been such a problem that the above X-address degenerate parallel test can not be carried out in the test including the redundant substitution of the faulty memory cell. Because, in the above degenerate X-address parallel test, it is impossible to judge which block the faulty memory cell belongs to, and the above column redundant substitution is that which is applied to two degenerate Y-addresses in the block, so that it is hard to simultaneously relief the different blocks.
For instance, in case of the semiconductor memory device of the 8-bit configuration, there is mainly adopted such a configuration that is convenient for the unit data of 8-bit to be read from/written to either the block A or B. Furthermore, for instance, in case of the semiconductor memory device of the 16-bit configuration, there is mainly adopted such a configuration that the Y-address data is provided with no block selection bit and 8-bit each of the unit data of 16 bit is read from/written to the blocks A and B. However, in case of the semiconductor device having no block selection bit, there was the problem that the degenerate X-address parallel test can not be executed. Because it is not possible to simultaneously read out two data of the different block to the same data bus pair. As the multiplex of the read/write data unit bit is strongly desired, so that the configuration without the block selection might form the main current in future as described above.
SUMMARY OF THE INVENTION
The present invention has been made in order to solve such problems as described above, and it is an object of the invention to provide a semiconductor memory device of which the test time can be shortened by widening the application range of the parallel test such that the parallel test becomes possible even in the test of the semiconductor memory device provided with neither the test including the redundant substitution nor the block selection.
In order to achieve the above object, according to the invention, there is provided a semiconductor memory device having a memory portion wherein the data read/write is carried out by means of an EVEN/ODD system provided with an EVEN subdata bus and an ODD subdata bus, the above semiconductor memory device comprising:
a column control means for simultaneously activating a plurality of columns which are subject to the degenerate substitution in the column redundant substitution;
a data read-out means for simultaneously reading out the data from a plurality of memory cells as selected by the above plurality of columns, the data read-out m

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