Semiconductor memory device having short refresh time

Details Semiconductor memory device having short refresh time Semiconductor memory device having short refresh time

2006-10-17

2006-10-17

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S203000, C365S210130

Reexamination Certificate

active

07123534

ABSTRACT:
A semiconductor memory device in which memory cells are arranged at intersections between the word lines and the bit lines includes a control unit for selecting, in a second half of a cycle in which a first word line is selected from the word lines to conduct a read or write operation for a first memory cell coupled with the first word line, a second word line other than the first word line and refreshing memory cells corresponding to the second word line. The memory cell includes an amplifier section including two driver transistors of which gate and drain electrodes are respectively cross-coupled with each other and a switch section including selector transistors coupling the amplifier section with the bit lines according to a selection signal on the bit line. Either one of each transistor and each selector transistor is an n-channel transistor or a p-type transistor.

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patent: 6773972 (2004-08-01), Marshall et al.
patent: 10-501363 (1995-05-01), None
patent: 2001-202775 (2000-01-01), None
patent: WO 95/33265 (1995-05-01), None

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