Semiconductor memory device having self-refresh mode

Details Semiconductor memory device having self-refresh mode Semiconductor memory device having self-refresh mode

2002-05-10

2003-08-05

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S228000

Reexamination Certificate

active

06603695

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a self-refresh mode.
2. Description of the Background Art
Conventionally, a dynamic random access memory (hereinafter referred to as DRAM) is provided with an address generating circuit that, in response to an instruction for execution of self-refresh, sequentially generates a plurality of address signals one by one, which are pre-allocated to a plurality of memory cell rows respectively, with a predetermined cycle, and designates memory cell rows to be refreshed by the generated address signals.
FIG. 11
is a block diagram showing the configuration of such an address generating circuit
150
. Referring to
FIG. 11
, address generating circuit
150
includes a constant current circuit
151
, a voltage converting circuit
152
, a voltage control oscillation circuit
153
, a count control signal generating circuit
154
, a trimming switching circuit
155
, five counting circuits
156
to
160
, a detection circuit
161
, and an address counter
162
.
Constant current circuit
151
generates constant current of a predetermined value, and outputs a constant voltage VBN of a value corresponding to the constant current. Voltage converting circuit
152
is activated in response to a self-refresh instruction signal SR being set to an activated level of a logic high or “H” level, and converts output voltage VBN of constant current circuit
151
into a constant voltage VB of a predetermined value. Voltage control oscillation circuit
153
is activated in response to self-refresh instruction signal SR being set to the activated level of “H” level, and generates a clock signal CLK having a cycle obtained by dividing a refresh cycle by an integer, in accordance with output voltage VB of voltage converting circuit
152
.
Count control signal generating circuit
154
includes, as shown in FIG.
12
, inverters
163
to
165
, a delay circuit
166
, an NAND gate
167
and an NOR gate
168
. Clock signal CLK generated at voltage control oscillation circuit
153
is input into one input node of each of NAND gate
167
and NOR gate
168
via inverter
163
, delay circuit
166
and inverter
164
, and is also input into the other input node of each of NAND gate
167
and NOR gate
168
. As shown in
FIG. 13
, delay circuit
166
includes an even number (six in
FIG. 13
) of inverters
171
to
176
connected in series. An output clock signal of NAND gate
167
is inverted at inverter
165
to be a count clock signal CK
1
. An output clock signal of NOR gate
168
is a determination clock signal CK
2
. Each of clock signals CK
1
and CK
2
has the same cycle as that of clock signal CLK, and both clock signals CK
1
and CK
2
are non-overlapped two-phase clock signals that are not set to the “H” level at a time.
Referring again to
FIG. 11
, trimming switching circuit
155
includes five fuses, and is activated by output voltage VBN of constant current circuit
151
, setting each of signals &phgr;
0
to &phgr;
4
to be at the “H” level or an “L (logic low)” level, depending on the state of each of the five fuses (i.e. whether or not each fuse blown). Signals &phgr;
0
to &phgr;
4
are applied to counting circuits
156
to
160
respectively.
Referring to
FIG. 14
, counting circuit
156
includes inverters
180
to
186
, transfer gates
187
to
189
, and clocked inverters
190
,
191
. Inverters
182
,
183
,
190
and
191
, and transfer gates
188
,
189
constitute a flip-flop
192
. Flip-flop
192
captures a level of an input terminal
192
a
when count clock signal CK
1
is at the “L” level, and outputs a signal of the captured level in response to count clock signal CK
1
being raised from the “L” level to the “H” level. Inverter
184
is connected between an output terminal
192
b
and input terminal
192
a
of flip-flop
192
. An output signal of inverter
180
is inverted at inverter
186
to be an output clock signal CY
0
of counting circuit
156
. Therefore, clock signal CY
0
is a signal obtained by frequency-dividing clock signal CK
1
by two.
Inverters
180
,
181
and transfer gate
187
constitute a preset circuit. Transfer gate
187
is rendered conductive while preset signal PR is at an activated level of “H” level, and a signal &phgr;
0
is applied to a latch circuit constituted by inverters
183
,
191
via inverter
180
and transfer gate
187
. This makes signal &phgr;
0
and output clock signal CY
0
be at the same logic level.
Counting circuit
157
is formed, as shown in
FIG. 15
, by removing inverter
181
from counting circuit
156
and adding NAND gates
193
,
194
, inverters
195
,
196
and a transfer gate
197
thereto. Moreover, flip-flop
192
operates in synchronization with output clock signal CY
0
of counting circuit
156
, in place of count clock signal CK
1
. Thus, output clock signal CY
1
of counting circuit
157
is a signal obtained by frequency-dividing output clock signal CY
0
of counting circuit
156
in the previous stage by two.
Inverters
180
,
195
,
196
, transfer gates
187
,
197
, and NAND gates
193
,
194
constitute a preset circuit. When preset signal PR is set to the “H” level while clock signal CY
0
is at the “H” level, transfer gate
197
is rendered conductive, and a signal &phgr;
1
is applied to a latch circuit constituted by inverters
182
and
190
via transfer gate
197
. When preset signal PR is set to the “H” level while clock signal CY
0
is at the “L” level, transfer gate
187
is rendered conductive, and signal &phgr;
1
is applied to a latch circuit constituted by inverters
183
and
191
via inverter
180
and transfer gate
187
. In either case, signal &phgr;
1
and output clock signal CY
1
have the same logic level.
Counting circuits
158
to
160
have the same configuration as that of counting circuit
157
. Counting circuit
158
outputs a clock signal CY
2
obtained by frequency-dividing output clock signal CY
1
of counting circuit
157
by two. Counting circuit
159
outputs a clock signal CY
3
obtained by frequency-dividing output clock signal CY
2
of counting circuit
158
by two. Counting circuit
160
outputs a clock signal CY
4
obtained by frequency-dividing output clock signal CY
3
of counting circuit
159
by two. Thus, output clock signals CY
0
to CY
4
of counting circuits
156
to
160
have frequencies twice, four times, eight times, sixteen times and thirty-two times, respectively, as much as the frequency of clock signal CK
1
. Moreover, the timing of rising edges of clock signals CY
0
to CY
4
can be changed by trimming switching circuit
155
.
As shown in
FIG. 16
, detection circuit
161
includes NAND gates
201
to
207
, an NOR gate
208
and an inverter
209
, in which NAND gates
205
and
206
constitute a flip-flop
210
. NAND gate
201
receives clock signals CY
0
to CY
2
, NAND gate
202
receives clock signals CY
3
and CY
4
, and NOR gate
208
receives output signals of NAND gates
201
and
202
. NAND gate
203
receives a determination clock signal CK
2
and a self-refresh instruction signal SR, and the output signal thereof is input into a reset terminal
210
b
of flip-flop
210
via inverter
209
. NAND gate
204
receives an output signal &phgr;
208
of NOR gate
208
and an output signal of inverter
209
, and an output signal of NAND gate
204
is input into a set terminal
210
a
of flip-flop
210
. An output signal of flip-flop
210
is a signal PHYS indicating a refresh cycle. NAND gate
207
receives an inversion output signal of flip-flop
210
and self-refresh instruction signal SR, and outputs a preset signal PR.
When self-refresh instruction signal SR is at the “L” level, the output signal of inverter
209
is fixed at the “L” level, resetting flip-flop
210
, and thus signal PHYS is set to the “L” level, whereas preset signal PR is set to the “H” level. When self-refresh instruction signal SR is at the “H” level, each of NAND gates
203
and
207
operates as an inverter. When

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