Semiconductor memory device having self refresh mode

Details Semiconductor memory device having self refresh mode Semiconductor memory device having self refresh mode

2000-08-25

2001-12-04

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S225700, C365S233100

Reexamination Certificate

active

06327208

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices and more particularly to a semiconductor memory device having a self refresh mode.
2. Description of the Background Art
FIG. 10
is a block diagram showing an overall configuration of a conventional dynamic random access memory (hereinafter, referred to as a DRAM). Referring to
FIG. 10
, the DRAM includes a POR (Power On Reset) circuit
31
, a self refresh circuit
32
, a clock generation circuit
33
, a row/column address buffer
34
, a row decoder
35
, a column decoder
36
, a memory mat
37
, a data input buffer
40
, and a data output buffer
41
. Memory mat
37
has a memory array
38
and a sense amplifier+input/output control circuit
39
.
In response to application of an external power supply potential VCC and an external ground potential VSS, POR circuit
31
outputs a signal /POR for resetting the DRAM. In response to external control signals /RAS, /CAS designating execution of refreshing, self refresh circuit
32
increments row address signals RA
0
to RAm (m is an integer of at least 0) in a predetermined cycle. Clock generation circuit
33
selects a prescribed operation mode based on external control signals /RAS, /CAS, /WE and thus controls the entire DRAM.
Row/column address buffer
34
generates row address signals RA
0
to RAm and column address signals CA
0
to CAm according to external address signals A
0
to Am, and applies signals RA
0
to RAm and CA
0
to CAm thus generated to row decoder
35
and column decoder
36
, respectively.
Memory array
38
includes a plurality of memory cells each storing 1-bit data. Each memory cell is arranged at a prescribed address determined by row and column addresses.
Row decoder
35
designates row addresses of memory array
38
according to row address signals RA
0
to RAm applied from row/column address buffer
34
or self refresh circuit
32
. Column decoder
36
designates column addresses of memory array
38
according to column address signals CA
0
to CAm applied from row/column address buffer
34
.
Sense amplifier+input/output control circuit
39
reads out data of a memory cell at a row address designated by row decoder
35
, and connects a memory cell at a column address designated by column decoder
36
to one end of a data input/output line pair IOP. The other end of data input/output line pair IOP is connected to data input buffer
40
and data output buffer
41
. In a writing mode, data input buffer
40
applies externally input data D
0
to Dn (n is an integer of at least 0) to selected memory cells through data input/output line pair IOP and rewrites data of the memory cells. In a reading mode, data output buffer
41
supplies read data Q
0
to Qn as an output from selected memory cells in response to an external control signal /OE.
FIG. 11
is a circuit diagram showing a configuration of DRAM memory mat
37
shown in FIG.
10
. Here, only a portion corresponding to 1/bit data DQ
0
is shown.
In
FIG. 11
, memory array
38
includes a plurality of memory cells MCs arranged in rows and columns, a word line WL provided for each row, and a pair of bit lines BL, /BL provided for each column. Each memory cell MC includes an N channel MOS transistor for accessing and a capacitor for storing information as is well known. One end of word line WL is connected to row decoder
35
.
Sense amplifier+input/output control circuit
39
includes a column selection line CLS, a column selection gate
42
, a sense amplifier
43
and an equalizer
44
which are provided for each column. Column selection gate
42
includes two N channel MOS transistors connected between bit lines BL, /BL and data input/output lines IO, /IO, respectively. The two N channel MOS transistors have their gates connected to column decoder
36
through column selection line CSL. When column selection line CSL is raised to a logical high or H level selected state by column decoders
36
, the two N channel MOS transistors are rendered conductive and thereby the pair of bit lines BL, /BL and the pair of data input/output lines IO, /IO are connected.
Sense amplifier
43
amplifies a small potential difference between the pair of bit lines BL, /BL to a power supply voltage VCC in response to sense amplifier activation signals SON, ZSOP attaining logical high and low or H and L levels, respectively. Equalizer
44
equalizes the potentials of bit lines BL, /BL to a bit line potential VBL in response to a bit line equalize signal BLEQ attaining an H level active state.
In the following, an operation of the DRAM shown in
FIGS. 10 and 11
will be described. In the writing mode, column selection line CSL in a line corresponding to column address signal CA
0
to CAm is raised to the H level selected state by column decoder
36
, and column selection gate
42
in the column is rendered conductive.
In response to signal /WE, data input buffer
40
applies externally applied write data to a bit line pair BL, /BL in the selected column through data input/output line pair IO, /IO. The write data is applied as a potential difference between bit lines BL, /BL. Then, word line WL in a row corresponding to row address signal RA
0
to RAm is raised to an H level selected state by row decoder
35
, and N channel MOS transistors of memory cells MCs in that row are rendered conductive. Electric charges of such an amount that corresponds to the potential of bit line BL or /BL are stored in the capacitor of a selected memory cell MC.
In the reading mode, bit line equalize signal BLEQ is first lowered to an L level to stop equalization of bit lines BL, /BL, and word line WL in a row corresponding to row address signal RA
0
to RAm is raised to an H level selected state by row decoder
35
. The potentials of bit lines BL, /BL are slightly changed according to the amount of electric charges in the capacitor of activated memory cell MC.
Then, sense amplifier activation signals SON, ZSOP are driven to H and L levels, respectively, thus activating sense amplifier
43
. When the potential of bit line BL is slightly higher than the potential of bit line /BL, the potential of bit line BL is raised to an H level and the potential of bit line /BL is lowered to an L level. Conversely, when the potential of bit line /BL is slightly higher than the potential of bit line BL, the potential of bit lines /BL is raised to an H level and the potential of bit line BL is lowered to an L level.
Then, column selection line CSL in a column corresponding to column address signal CA
0
to CAm is raised to the H level selected state by column decoder
36
and thereby column selection gate
42
in the column is rendered conductive. Data of bit line pair BL, /BL in the selected column is applied to data output buffer
41
through column selection gate
42
and data input/output line pair IO, /IO. Data output buffer
41
supplies the read data as an output in response to signal /OE.
In a self refresh mode, row address signal RA
0
to RAm generated by self refresh circuit
32
is applied to row decoder
35
instead of row address signal RA
0
to RAm from row/column address buffer
34
. Row decoder
35
drives one word line WL of a plurality of word lines WL in memory array
38
to an H level selected state according to row address signal RA
0
to RAm from self refresh circuit
32
. Similarly to the reading mode, sense amplifier
43
and equalizer
44
are driven in synchronization with row decoder
35
, and data once read out from each memory cell MC to bit line pair BL, /BL is written to memory cell MC again. Row address signal RA
0
to RAm from self refresh circuit
32
is incremented in a prescribed cycle. Therefore, until a designation to stop self refreshing is issued, data in memory cells MCs in a plurality of rows included in memory array
38
is sequentially refreshed for each row.
FIG. 12
is a block diagram showing a configuration of self refresh circuit
32
. In
FIG. 12
, self refresh circuit
32
includes a CBR determination circuit
51
, a basic cycle generatio

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