Semiconductor memory device having selective and simultaneous wr

Details Semiconductor memory device having selective and simultaneous wr Semiconductor memory device having selective and simultaneous wr

1991-03-12

1994-02-08

Sikes, William L.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36518912, 365202, G11C 700

Patent

active

052854132

ABSTRACT:
A semiconductor memory device includes a memory cell array including plural memory cells arranged in an array, and plural bit lines and word lines connected to said memory cells respectively, a simultaneous writing data bus which is supplied with simultaneous writing data, and a simultaneous data wiring circuit which responsive to control signals, connects the simultaneous writing data bus with bit lines which are connected to the memory cells connected under the same word line in the memory cell array. By constructing the memory as above, the same data can be written in all the memory cells under the same word line within a single cycle, and compared to the prior art which has to write in by selecting bit line pairs each time by a column decoder, the operational speed can be remarkably enhanced.

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