Semiconductor memory device having selection circuit for arbitra

Details Semiconductor memory device having selection circuit for arbitra Semiconductor memory device having selection circuit for arbitra

1998-03-06

2000-03-07

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

365233, G11C 800

Patent

active

060349042

ABSTRACT:
A semiconductor memory device includes a control circuit, a test mode control circuit, an internal period setting circuit and an address latch circuit. The control circuit detects whether test mode is designated or not. The test mode control circuit detects whether or not self disturb test mode is designated. The internal period setting circuit repeatedly generates a clock signal of a prescribed period when the test mode and the self disturb test mode are designated. Simultaneously, the address latch circuit latches an address at a fall of a row address strobe signal. The row decoder is activated in response to the clock signal, and repeatedly sets the word line corresponding to the latched address to the selected state.

REFERENCES:
patent: 5717652 (1998-02-01), Ooishi
patent: 5875153 (1999-02-01), Hii et al.
patent: 5883843 (1999-03-01), Hii et al.

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