Semiconductor memory device having row repair circuitry

Details Semiconductor memory device having row repair circuitry Semiconductor memory device having row repair circuitry

2002-01-04

2004-03-09

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000, C365S230060, 37, 37

Reexamination Certificate

active

06704226

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2001-25144, filed on May 9, 2001, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND
1. Field of Invention
The inventions disclosed herein generally relate to a semiconductor memory device having a capacity of redundancy. More particularly, they relate to a semiconductor memory device having row repair circuitry in which defective wordlines are substituted with redundant wordlines regardless of locations of memory blocks. A predetermined number of the redundant wordlines is arranged in each memory block.
2. General Background and Related Art
It is usual that various kinds of defects are generated throughout a manufacturing process for a semiconductor memory device (e.g., a DRAM), thereby causing the memory device to malfunction and reducing the yield of its manufacturing process. Even one defect over a cell array in the semiconductor memory device may easily interrupt normal operations such as data read-out and write-in. For this reason, it is known to substitute defective memory cells with additionally prepared memory cells (i.e., redundant or spare memory cells), thereby increasing the yield of manufacture and reliability of the memory device. When one or more defective memory cells are detected by a test operation, the defective memory cells are substituted with the redundant memory cells that are arranged in the unit of row or column in a memory cell array of the memory device, thereby allowing the memory device to be used even though it has some defective cells.
FIG. 1
is a schematic representation of a DRAM. Consider a conventional 64M (64 megabits; M=2
20
) DRAM constructed of four memory banks MB
0
, MB
1
, MB
2
and MB
3
. Each memory bank has a storage capacity of 16M and an associated peripheral block PBL in which input/output pads are arranged and which includes input/output buffers and multiplexers assigned to the input/output pads. The peripheral block PBL where pads for address and control signals are positioned includes control signal buffers and address buffers being coupled to their corresponding pads, and further a control logic unit and a command state machine. Column control logic blocks CCL
0
~CCL
3
each assigned to their corresponding memory banks have Y-decoders (or column decoders), drivers and data bus sense amplifiers to write data in memory cells or to read data from memory cells. Row control logic blocks assigned to their corresponding memory banks and which include X-decoders (or row decoders) and logic circuits for driving wordlines.
Each memory block has the predetermined number of redundant wordlines assigned thereto exclusively. According to the configurations of redundancy in this manner, since the predetermined number of redundant wordlines restricts defective wordlines yet repairable, the device shown in
FIG. 1
may have a limitation to enhance the efficiency of repairing the defective wordlines (or memory cells) and to increase an extension facility of repairing. For instance, when the number of defective memory cells is greater than that of redundant wordlines in the memory bank MB
1
, it is impossible to repair the defective wordlines in excess of the capacity of the redundant wordlines therein.
SUMMARY
Among the various inventions described in this patent document, there is described a semiconductor memory device capable of enhancing the efficiency of repairing defective memory cells. There is also described a semiconductor memory device capable of repairing defective wordlines regardless of locations of defective wordlines.
There is provided a semiconductor memory device having a row repair function, including a plurality of memory blocks each having a predetermined number of redundant wordlines, a plurality of row repair fuse boxes arranged so that the same number are associated with each memory block, the number of the fuse boxes being identical to that of the redundant wordlines, and repair means to replace defective wordlines with the redundant wordlines. The redundant wordlines corresponds to the row repair fuse boxes each by each.
The inventions claimed will be better understood from the following detailed description of a presently preferred exemplary embodiment, described with reference to the accompanying drawings, and the scope of which will be set forth in the appended claims.


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