Semiconductor memory device having row repair circuitry

Details Semiconductor memory device having row repair circuitry Semiconductor memory device having row repair circuitry

2001-06-27

2002-12-24

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230030, C365S225700

Reexamination Certificate

active

06498756

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2000-36158, filed on Jun. 28, 2000 and No. 2001-24263, filed on May 4, 2001, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention generally relates to a semiconductor memory device having a capacity of redundancy, and more particularly to a semiconductor memory device with row repair circuitry by which defective wordlines are substituted with redundant wordlines regardless of locations of cell array blocks, the redundant wordlines being arranged in a specific cell array block.
BACKGROUND OF THE INVENTION
It is usually occasional that various kinds of defects are generated throughout a manufacturing process for a semiconductor memory device (e.g., a DRAM), causing the memory device to be in a malfunction and reducing a yield thereof. Even one defect over a cell array in the semiconductor memory device may easily turn it out of normal operations such as data read-out and write-in. For this reason, it is recommended to substitute defective memory cells with additionally prepared memory cells (i.e., redundant or spare memory cells) in correspondence with their addresses, i.e., “redundancy”, increasing a product yield and reliability of the memory device. When one or more defective memory cells are detected by a test operation, the defective memory cells are substituted with the redundant memory cells that are arranged in the unit of row or column in a memory cell array of the memory device, without abandoning the memory device even though it has the defective cells.
In a conventional 64 M (64 megabits; M=2
20
) DRAM constructed of four memory banks, each bank has the storage capacity of 16 M with being formed of a plurality of memory blocks, as shown in
FIG. 1
, and peripheral block PBL in which input/output pads are arranged includes input/output buffers and multiplexers assigned to the input/output pads. The peripheral block PBL in which pads for address and control signals are positioned includes control signal buffers and address buffers being coupled to their corresponding pads, and further a control logic unit and a command state machine. Column control logic blocks CCL
0
~CCL
3
each assigned to their corresponding memory banks have Y-decoders (or column decoders), drivers and data bus sense amplifiers to write data in memory cells or to read data from memory cells. Row control logic blocks RCL
0
~RCL
3
each assigned to their corresponding memory banks include X-decoders (or row decoders) and logic circuits for driving wordlines.
And, each of the memory blocks has a predetermined number of redundant wordlines being assigned thereto exclusively. According to the fashion of redundancy in this manner, since defective wordlines yet repairable is limited by the predetermined number of redundant wordlines, the device shown in
FIG. 1
may come up with a limitation to enhance the efficiency of repairing the defective wordlines (or memory cells). For instance, when the number of defective memory cells is greater than that of redundant wordlines in the memory bank MB
1
, it is impossible to repair the defective wordlines in excess of the capacity of the redundant wordlines therein.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a semiconductor memory device capable of enhancing the efficiency of repairing defective memory cells.
It is another object of the present invention to provide a semiconductor memory device capable of repairing defective wordlines without positional restriction of defective wordlines.
In order to attain the above objects, according to an aspect of the present invention, there is provided a semiconductor memory device having a function of row repair, including a plurality of memory blocks where at least one of them includes a predetermined number of redundant wordlines, the predetermined number of row repair fuse boxes being divisionally arranged to be the same with the number of the memory blocks, and repair means to replace defective wordlines with the redundant wordlines, each redundant wordline corresponds to one of the row repair fuse boxes respectively.
The present invention will be better understood from the following detailed description of the exemplary embodiment thereof taken in conjunction with the accompanying drawings, and its scope will be pointed out in the appended claims.


REFERENCES:
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patent: 5978931 (1999-11-01), Kirihata et al.
patent: 6094382 (2000-07-01), Choi et al.
patent: 6233183 (2001-05-01), Kim et al.
patent: 6252808 (2001-06-01), Yoo
patent: 6304498 (2001-10-01), Ikeda

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