Semiconductor memory device having row path control circuit...

Details Semiconductor memory device having row path control circuit... Semiconductor memory device having row path control circuit...

2006-06-27

2006-06-27

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S230060, C365S230080, C365S236000

Reexamination Certificate

active

07068558

ABSTRACT:
A semiconductor memory device having a row path control circuit for reducing a peak current. The semiconductor memory device including: a bank controller for activating the bank signal as a first and a second bank driving signals; an inner address counter for generating an internal address in response to the refresh signal; a row address latch for selecting one of the internal address and the inputted address; a first decoder for decoding the row address in response to the first bank driving signal; a second decoder for decoding the row address in response to the second bank driving signal; a first row controller for activating a first amplifier enable signal in response to the first bank driving signal; a second row controller for activating a second amplifier enable signal in response to the second bank driving signal; and a amplifier for amplifying memory cell data of the activated word line.

REFERENCES:
patent: 6744685 (2004-06-01), Mizugaki

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