Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-03-27
2002-10-01
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S189020
Reexamination Certificate
active
06459630
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-088963, filed Mar. 28, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, for example, a dynamic random access memory (DRAM), and in particular, to a semiconductor memory device having a function of switching data lines based on a data line-shifting redundancy method to relieve defective columns and testing redundancy cells.
A semiconductor memory device such as a DRAM is provided with redundancy memory cells in addition to normal memory cells and comprises a redundant circuit to relieve some defective cells randomly present in the normal memory cells. The defective cells are replaced with redundant rows or columns using as relieved units defective rows or columns in which the defective cells are present.
In a normal redundant circuit, a fuse circuit storing defective address data is mounted on a memory chip. Address data input to the memory are compared with data stored in the fuse circuit, and when the data are equal, a replacement signal is generated to select redundant rows or columns for defective rows or columns.
Then, the defective column relieve method is focused on. When the defective columns are correlated with the redundant columns on a one-to-one correspondence, the scale of the column redundant circuit must be increased if an attempt is made to increase defective column relieve efficiency.
Thus, as a method for making it possible to efficiently relieve defective columns with a smaller-scale circuit, a data line-shifting redundant circuit based on shifting of data lines is disclosed, for example, in Jpn. Pat. Appln. KOKAI Publication No. 3-176899 and No. 5-101648.
In the data line-shifting redundant circuit disclosed in these publications, when a defective address corresponding to a defective column is input, a data line that outputs readout data corresponding to this defective column is replaced with an adjacent normal data line for use. For the addresses following this defective address, data lines are subjected to shift control so as to be sequentially shifted in such a manner that only normal data lines including a spare data line arranged at an end of the array of the data lines are connected to a data I/O line.
A conventional column redundant circuit provided in a DRAM will be described below.
FIG. 1
is a block diagram showing an example of the configuration of a conventional column redundant circuit.
A switching circuit
11
switches a connection to a memory cell array
12
between a first group of data lines I/O LINES #
1
and a second group of data lines I/O LINES #
2
in order to transfer readout/write data to and from the memory cell array
12
. The switching circuit
11
has its operation controlled by means of a switch status signal issued by an analyzer
13
according to a column address signal CA.
FIG. 2
is a block diagram showing an example of a configuration where a data line-shifting redundant circuit is provided as the column redundant circuit in FIG.
1
.
The switching circuit
11
is controlled by means of the switch status signal so as to switch a connection path between the first group of data lines I/O LINES #
1
and the second group of data lines I/O LINES #
2
based on the data line shifting method.
Repeated structures (the portions enclosed by dot lines) in the switching circuit
11
are each called an I/O unit
11
A.
Each I/O unit
11
A has an I/O number that is information on itself. The I/O number is often an address.
The switch status signal output from the analyzer
13
according to each column address signal CA is represented by a shift number corresponding to the I/O number. Thus, a fuse circuit is provided which is composed of a plurality of fuse elements storing information (reconnection information) on the correlationship between the column address signals CA and the switch status signals.
FIG. 2
shows an operational state in which a shift number
4
is issued as the switch status signal.
The I/O units
11
A having an I/O number equal to or larger than the shift number issued by the analyzer
13
performs a shift operation such that each relevant data line of the group of data lines I/O LINES #
2
is connected to one of the group of data lines I/O LINES #
1
which is adjacent to another of the data lines I/O LINES
1
which corresponds to the first data line. In
FIG. 2
, all the I/O units
11
A having an I/O number of 4 or more execute reconnections.
In the data line-shifting redundant circuit in
FIG. 2
, a start point for data line shifting which corresponds to a defective column address is stored in a fuse element in the fuse circuit
14
. In this configuration, however, with a large number of data lines of the first and second groups, a large number of selection signal lines (shift number transfer lines) for shift-controlling the data lines are required, thus complicating the configuration of the switching circuit
11
for shifting the data lines.
Thus, an improved data line-shifting redundant circuit that requires a reduced number of selection signal lines for shift-controlling the data lines has been proposed. This data line-shifting redundant circuit has a configuration such as that shown in FIG.
3
.
This circuit differs from the data line-shifting redundant circuit shown in
FIG. 2
in that the I/O numbers provided for the I/O units
11
A are not the addresses but numbers varying with groups.
In this case, the plurality of I/O units
11
A can be classified into groups each of which has the same redundancy status despite the variation of the column address CA.
The circuit additionally has an I/O numbering circuit
15
for providing numbers varying with the group, as the I/O numbers provided to the I/O units
11
A. For example, the plurality of I/O units
11
A are represented as lower units having lower I/O numbers (in the left of the figure) and higher units on the opposite side (in the right of the figure).
In addition to the fuse circuit
14
having the information (reconnection information) on the correlationship between the column address signals CA and the switch status signals, a fuse circuit
16
is provided which has a plurality of fuse elements storing information (reconnection information) on the correlationship between the I/O units
11
A and the I/O numbers.
FIG. 3
shows an operational state in which a shift number 1 is issued as the shift status signal. This configuration makes it possible to reduce the varying range of the value of the shift number, thus reducing the number of wires for transmitting the shift status to the I/O units
11
A.
In a DRAM having the data line-shifting redundant circuit, it is assumed that the circuit is provided with a forced access mode for forcibly accessing memory cells regardless of the storage statuses of the fuse circuits storing the reconnection information. A mode in which memory cells are accessed while reconnections are being carried out in order to relieve defective memory cells is called an “normal access mode”.
If the forced access mode is added to the circuit, it can be implemented using a certain method. A specific example of a circuit with the forced access mode added thereto is the configuration shown in
FIGS. 4 and 5
.
The circuit in
FIG. 4
is a DRAM having the data line-shifting redundant circuit in
FIG. 3
, the DRAM being configured so that in a test mode, the switch status signal determined by the column address CA is neglected, while the switch status signal with the shift number 4 is output to the I/O units
11
A. In this case, no I/O unit
11
A has a shift number equal to or larger than 4, reconnections are not carried out, that is, reconnections are forcibly disabled (forcibly disabling status), thus making irrelevant the storage statuses of the fuse circuits having the reconnection information.
On the other hand, the circuit in
FIG. 5
is a DRAM having
Haga Ryo
Nakayama Atsushi
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Nguyen Tan T.
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