Semiconductor memory device having refreshing function

Details Semiconductor memory device having refreshing function Semiconductor memory device having refreshing function

2001-10-09

2003-09-30

Le, Thong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S233100, C365S226000

Reexamination Certificate

active

06628559

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a circuit configuration of a refreshing control circuit of a DRAM (Dynamic Random Access Memory) with a complete hidden refreshing function.
2. Description of the Background Art
Information stored in a DRAM with a complete hidden refreshing function is held by accumulating charges in a capacitor provided in a memory cell.
To prevent the stored information from being destroyed by a leak current, it is therefore necessary to periodically perform what is called a refreshing operation. The refreshing operation is performed by sequentially selecting word lines provided for rows of memory cells, reading and amplifying micro signals stored in all the memory cells on a selected word line, and executing rewriting. Even if the voltage of a storage node in a memory cell drops due to a leak current or the like, it is reproduced to an initial value.
By continuously sequentially selecting all the word lines, information stored in all the memory cells is reproduced, and storage information of the entire chip is held.
When the maximum refresh interval at which data of all the memory cells can be guaranteed is set as “trefmx” and “n” denotes the number of word lines, to refresh the word lines in refresh cycles tcrf at regular intervals so as to prevent stored information from being destroyed by a leak current or the like, tcrf≦trefmx
has to be set.
FIG. 21
is a block diagram of a row selection control circuit
2000
for performing a conventional refreshing control included in a row decoder.
Row selection control circuit
2000
has a refresh timer
100
, a refresh address generating circuit
200
, and an internal address generating circuit
300
.
Refresh timer
100
is a circuit for generating a refresh clock signal RCLK for specifying a cycle tcrf of executing the refreshing operation.
Refresh address generating circuit
200
is a circuit for receiving refresh clock signal RCLK, generating a refresh address in the refreshing operation, and outputting the refresh address to internal address generating circuit
300
. In the refreshing operation, synchronously with refresh clock signal RCLK, counting of a row address for refreshing or the like is performed.
Internal address generating circuit
300
selects either an external address as an input signal or the refresh address and generates an internal address to designate a row address in a memory cell array.
To normally execute the refreshing operation, refresh timer
100
therefore has to oscillate refresh clock signal RCLK at a predetermined frequency (cycle) so as to designate each of word lines to be sequentially refreshed in accurate cycles determined according to the refresh cycle.
In refresh timer
100
in which a ring oscillator or the like is usually used, however, for example, when the power is turned on, it takes some time until the power becomes stable. Consequently, an oscillation period is unstable.
In the conventional refreshing control circuit configuration, therefore, since unstable refresh clock signal RCLK is supplied to refresh address generating circuit
200
, there is the possibility of causing an erroneous operation such that a refresh address is not accurately generated.
SUMMARY OF THE INVENTION
An object of the invention is to provide a semiconductor device capable of preventing an erroneous operation in a refreshing control in a period where the state of refresh clock signal RCLK is unstable, typically at power-on.
A semiconductor memory device of the invention has: a memory array having a plurality of memory cells arranged in a matrix; a refresh timer for generating a refresh clock having a predetermined refresh cycle; a refresh executing circuit for sequentially refreshing the plurality of memory cells part by part on the basis of the cycle of the refresh clock; and a refreshing control circuit disposed between the refresh timer and the refresh executing circuit, for stopping transmission of the refresh clock from the refresh timer to the refresh executing circuit in a predetermined period in which the cycle of the refresh clock is unstable.
According to the semiconductor memory device, by providing the refresh control circuit between the refresh timer and the refresh executing circuit, the transmission of the refresh clock to the refresh executing circuit can be stopped in the predetermined period in which the cycle of the refresh clock is easy to become unstable. Thus, an erroneous operation of the circuit can be prevented.
Preferably, the refreshing control circuit sets a period which is a predetermined time elapsed since an operation source voltage of the refresh timer is started to be applied as the predetermined period.
Consequently, the transmission of the unstable refresh clock can be stopped in the predetermined time since the operation source voltage of the refresh timer is started to be applied.
Particularly, the refreshing control circuit includes: a first power-on reset circuit for generating a first initialization control signal which is activated when the operation source voltage exceeds a first threshold voltage at power-on; a delay circuit for delaying the first initialization control signal from the power-on reset circuit; and a logic circuit for forcedly fixing a signal level of the refresh clock until the first initialization control signal delayed by the delay circuit is activated.
Since the refresh control circuit includes the power-on reset circuit for receiving the operation source voltage and outputting the initialization control signal, the delay circuit for delaying the initialization control signal, and the logic circuit for forcedly fixing the signal level of the refresh clock until the initialization control signal delayed by the delay circuit is activated, the refresh clock can be stopped until the initialization control signal delayed by the delay circuit is activated.
Particularly, the semiconductor memory device further includes an internal circuit whose circuit state is initialized at the power-on, and initialization of the circuit state in the internal circuit is executed on the basis of the first initialization control signal from the first power-on reset circuit.
The power-on reset circuit can be used as a circuit dedicated to the refresh control circuit or can be commonly used by other internal circuits.
Particularly, the semiconductor memory device further includes: a second power-on reset circuit for generating a second initialization control signal which is activated when the operation source voltage exceeds a second threshold voltage at the power-on; and an internal circuit whose circuit state is initialized in response to the second initialization control signal.
By providing the power-on reset circuit also used by other internal circuits and the power-on reset circuit used for the refresh control circuit separately, the rising of the initialization control signal of each circuit can be independently designed.
Particularly, the delay circuit has: a plurality of signal routes arranged in parallel and having different signal propagation times; and a selection circuit for transmitting the first initialization control signal to one of the plurality of signal routes.
By having the plurality of signal routes of different signal propagation times and the selection circuit for transmitting the signal to one of the plurality of signal routes, the delay circuit can vary the delay time.
Particularly, the selection circuit has a distribution switch selectively formed between a node to which the first initialization control signal is transmitted and the plurality of signal routes.
With the configuration that the selection circuit has the distribution switch selectively formed between the plurality of signal routes having different signal propagation times, the delay time can be changed also in the process of manufacturing a wafer by using a masking process.
Particularly, the selection circuit has a fuse element which can be blown from the ou

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