Semiconductor memory device having refresh mode and method...

Details Semiconductor memory device having refresh mode and method... Semiconductor memory device having refresh mode and method...

2008-06-28

2010-12-07

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S230060, C365S230090

Reexamination Certificate

active

07848168

ABSTRACT:
A semiconductor memory device can control the toggling of signals corresponding to internal addresses during an auto-refresh mode. The semiconductor memory device includes an internal address generator configured to generate a plurality of first word line driving information signals and a plurality of first to seventh address information signals, which are sequentially activated in response to a driving signal and a refresh signal, a toggle controller configured to generate first and second toggle control signals in response to the third to sixth address information signals during an auto-refresh mode or a self-refresh mode, and a driving controller configured to generate a plurality of bit line driving signals and a plurality of second word line driving information signals corresponding to the first to third and seventh address information signals in response to the first and second toggle control signals.

REFERENCES:
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patent: 7248525 (2007-07-01), Sato et al.
patent: 2002/0191467 (2002-12-01), Matsumoto et al.
patent: 2007/0086266 (2007-04-01), Freebern et al.
patent: 2002-203389 (2002-07-01), None
patent: 1993-0024012 (1993-12-01), None
patent: 10-0276386 (2000-09-01), None
patent: 2004-0079748 (2004-09-01), None

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