Semiconductor memory device having refresh circuits

Details Semiconductor memory device having refresh circuits Semiconductor memory device having refresh circuits

1994-12-14

1996-05-14

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Data refresh

365203, G11C 700

Patent

active

055174540

ABSTRACT:
A semiconductor memory device including dynamic memory cells for which refresh operation is required, wherein one fundamental cycle consists of a normal operation for carrying out writing or reading into or from the memory cells and a refresh operation. This semiconductor memory device comprising: a refresh signal generating circuit supplied with a clock signal to generate a refresh signal indicating start of refresh; a count signal generating circuit supplied with the clock signal to generate a count signal required for selection of a memory cell to be refreshed, a refresh counter circuit supplied with the refresh signal and the count signal to select a word line and a bit line to which a memory cell to be refreshed is connected; and a precharge circuit supplied with the refresh signal to carry out precharge of the bit line for refresh.

REFERENCES:
patent: 4870622 (1989-09-01), Aria et al.
patent: 4943960 (1990-07-01), Komatsu et al.
patent: 5343430 (1994-08-01), Furuyama

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