Semiconductor memory device having redundant memory cells

Details Semiconductor memory device having redundant memory cells Semiconductor memory device having redundant memory cells

1993-10-26

1994-10-25

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 36523006, G11C 700

Patent

active

053595599

ABSTRACT:
The described embodiments of the present invention provide a method in which the circuit configuration of redundancy circuitry in a random access memory can be simplified and the setting operation of the address of the defective memory cell is also simplified. In one described embodiment, the redundant circuit includes a fuse decoder (11), which functions as the address-generating circuit for the address of the defective memory cell, and a latch circuit (21). A write operation to the defective memory cell on the write port containing the fuse decoder (11) causes the address of the defective cell to be stored in the latch circuit. Each input/output port, except the input port using the fuse decoder, includes a comparator (22) for comparing the address for an operation on the respective port to the address stored in the latch circuit. A timing logic circuit (23) responds to a coincident signal generated by the comparator by providing signals which enable access to the redundant memory cell rather that the defective memory cell.

REFERENCES:
patent: 4757474 (1988-07-01), Fukushi et al.
patent: 4817056 (1989-03-01), Furutani et al.
patent: 4881202 (1989-11-01), Tsujimoto et al.
patent: 4947375 (1990-08-01), Gaultier et al.
patent: 5047983 (1991-09-01), Iwai et al.

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