Semiconductor memory device having redundant decoder with subtan

Static information storage and retrieval – Read/write circuit – Differential sensing

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36518909, G11C 702

Patent

active

058154531

ABSTRACT:
A redundant decoder has a charge line, a plurality of fuse elements connected to the charge line and selectively broken for storing a first address assigned to a defective column group of memory cells and a plurality of switching transistors connected between the fuse elements and a ground line and gated with internal address signals representative of a second address assigned to a column group of memory cells to be accessed, and compares the first address with the second address to see whether or not the defective column group is accessed; when the defective column group is accessed, all of the switching transistors are turned off, and an output circuit generates internal control signals on the basis of the potential level on the charge line so as to replace the defective column group with a redundant column group; when a non-defective column group is accessed, at least one current path is provided from the charge line through the non-broken fuse element and the switching transistor to the ground line, and the output circuit does not produce the internal control signal; and a current mirror circuit is connected between the charge line and the output circuit so as to prevent the output circuit from the resistance of the series of the non-broken fuse element and the associated switching transistor.

REFERENCES:
patent: 5699306 (1997-12-01), Lee et al.

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