Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-09-27
2003-03-11
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230030, C365S189040
Reexamination Certificate
active
06532181
ABSTRACT:
This application claims the benefit of priority under 35U.S.C. §119 of Japanese Patent Applications Nos. H11-156255, filed on, Jun. 3, 1999, and 2000-65398, filed on Mar. 9, 2000, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of The Invention
The present invention relates generally to an electrically rewritable semiconductor memory, such as an EEPROM. More specifically, the invention relates to a semiconductor memory having a redundant circuit for replacing a defective memory cell.
2. Description of The Related Background Art
In typical large scale semiconductor memories, a redundant circuit system for relieving a device having a certain range of defective memory cells is adopted in order to improve producing yields. The redundant circuit systems include three types, i.e., a column redundant circuit for replacing a defective bit line with a spare bit line, a row redundant circuit for replacing a defective word line with a spare word line, and a combination thereof.
A memory of a redundant circuit system has a defective address storing circuit, such as a fuse circuit, for nonvolatilisably storing a defective address. Then, the coincidence of an input address with a defective address is detected to output a coincidence detection output. In response to the coincidence detection output, the memory cell of the defective address is replaced with a memory cell of a redundant circuit.
However, in conventional EEPROMs, the relief efficiency using the redundant circuit is not high. Because it is not possible to cope with a plurality of defective columns or rows even if redundant circuits corresponding to one column or one row are arranged at the end portion of a memory cell array. In addition, even if redundant circuits corresponding to one column or one row are arranged at the end portion of the memory cell, there is a strong possibility that the redundant circuits themselves at the end portion of the cell array will be defective. This also lowers the relief efficiency.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a nonvolatile semiconductor memory comprising:
a memory cell array having electrically rewritable memory cells, the memory cell array being divided into a plurality of banks, each of the banks having a plurality of memory blocks, each of the memory blocks being the minimum unit for a data erase operation;
a memory cell array control circuit which controls the memory cell array so that while a data write operation or data erase operation is carried out in one of the banks, a data read operation can be carried out in the other banks;
a redundant cell array which has one or more spare blocks and which is provided independently of the banks to relieve a defective memory cell of the memory cell array by substituting the spare block for a defective memory block in any of the blocks, the defective memory block being the memory block including the defective memory cell;
a defective address storing circuit which stores a defective block address of the defective memory block; and
a redundant cell array control circuit which controls the redundant cell array so that the memory block is active when an access block address to be accessed in the memory cell array in the data write or erase operation or the data read operation does not coincide with the defective block address in the defective address storing circuit, whereas the spare block is active when the access block address coincides with the defective block address in the defective address storing circuit.
According to another aspect of the present invention, a nonvolatile semiconductor memory comprising:
a memory cell array having electrically rewritable memory cells, the memory cell array being divided into a plurality of banks, each of the banks having a plurality of memory blocks, each of the memory blocks being the minimum unit for a data erase operation;
a memory cell array control circuit which controls the memory cell array so that while a data write operation or data erase operation is carried out in one of the banks, a data read operation can be carried out in the other banks;
a redundant cell array which has one or more spare blocks and which is provided to relieve a defective memory cell of the memory cell array by substituting the spare block for a defective memory block in any of the blocks, the defective memory block being the memory block including the defective memory cell;
a defective address storing circuit which stores a defective block address of the defective memory block; and
a redundant cell array control circuit which controls the redundant cell array so that the memory block is active when an access block address to be accessed in the memory cell array in the data write or erase operation or the data read operation does not coincide with the defective block address in the defective address storing circuit, whereas the spare block is active when the access block address coincides with the defective block address in the defective address storing circuit.
According to a further aspect of the present invention, a nonvolatile semiconductor memory comprising:
a memory cell array having electrically rewritable memory cells, the memory cell array being divided into a plurality of banks, each of the banks having a plurality of memory blocks, each of the memory blocks being the minimum unit for a data erase operation;
a memory cell array control circuit which controls the memory cell array so that while a data write operation or data erase operation is carried out in one of the banks, a data read operation can be carried out in the other banks;
a redundant cell array which has one or more spare blocks to relieve a defective memory cell of the memory cell array, a memory size of the spare block is the same as that of the memory block;
a defective address storing circuit which stores a defective block address of the memory cell array; and
a redundant cell array control circuit which controls the redundant cell array so that the memory block is active when an access block address to be accessed in the memory cell array in the data write or erase operation or the data read operation does not coincide with the defective block address in the defective address storing circuit, whereas the spare block is active when the access block address coincides with the defective block address in the defective address storing circuit.
REFERENCES:
patent: 4914632 (1990-04-01), Fujishima et al.
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5287310 (1994-02-01), Schreck et al.
patent: 5410680 (1995-04-01), Challa et al.
patent: 5438546 (1995-08-01), Ishac et al.
patent: 5677880 (1997-10-01), Horiguchi et al.
patent: 5689465 (1997-11-01), Sukegawa et al.
patent: 5867430 (1999-02-01), Chen et al.
patent: 5905673 (1999-05-01), Khan
patent: 0 561 131 (1993-09-01), None
patent: 0 745 995 (1995-05-01), None
Honda Yasuhiko
Kato Hideo
Kuriyama Masao
Saito Hidetoshi
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Le Thong
Nelms David
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