Semiconductor memory device having redundant circuit

Details Semiconductor memory device having redundant circuit Semiconductor memory device having redundant circuit

1993-02-23

1994-03-29

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

365200, 36518405, 36523003, 36523006, G11C 2900

Patent

active

052991644

ABSTRACT:
An internal row address signal output from an address buffer is supplied to first and second row partial decoders. A programming circuit is programmed to store information indicating whether the redundant function is used or not and a defective address corresponding to a defective main word line or defective memory cell in a main memory cell array. The defective row address and the internal row adders signal are compared with each other by the programming circuit and the spare decoder, a control signal corresponding to the coincidence
on-coincidence of the compared row addresses is output, and a partial decode signal of the internal row address signal is output when the compared row addresses coincide with each other. The second partial decoder receives a control signal output from the spare decoder and outputs a partial decode signal of the internal row address signal when the control signal indicates the non-coincidence of the compared row addresses. The partial decode signals output from the first and second row partial decoders are supplied to the main row decoder which in turn selects one of main word lines in the main memory cell array. The partial decode signal output from the spare decoder is supplied to a spare row decoder which in turn selects one of spare word lines in a spare memory cell array.

REFERENCES:
patent: 4656610 (1987-04-01), Yoshida et al.
patent: 4914632 (1990-04-01), Fujisuima et al.
patent: 4918662 (1990-04-01), Kondo
patent: 4987560 (1991-01-01), Hamano et al.
patent: 5083294 (1992-01-01), Okajima
patent: 5124948 (1992-06-01), Takizawa et al.
patent: 5243570 (1993-09-01), Saruwatari

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