Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-08-22
2003-12-23
Le, Thong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S230060
Reexamination Certificate
active
06667915
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a redundancy circuit for relieving a defective memory cell.
DESCRIPTION OF THE BACKGROUND ART
In recent years, it has been essential for a semiconductor memory device with increasing capacity to have a redundancy circuit mounted therein to improve yields of products. The redundancy circuit is provided for replacing and relieving a defective memory cell, which is detected by an operation test, with a spare memory cell provided as an extra. Information related to the process of relieving the defective memory cell is programmed into the redundancy circuit and stored inside in a non-volatile manner.
The information programmed in the redundancy circuit includes a defective address indicating an address of a defective memory cell. At the time of using, when an access to the defective memory cell is required, the redundancy circuit is used in place of the defective memory cell to execute data reading and data writing.
Such a configuration allows the entire semiconductor memory device to normally operate using the redundancy circuit constituted by a spare memory cell, even if a defective memory cell occurs due to a defect at manufacturing. This allows secured yields of products.
However, the operation test for the semiconductor memory device is executed at different stages, such as a wafer test executed in a wafer state after fabrication of the wafer, and a product test executed in a product state after the subsequent step of assembling. In particular, the product test is performed after execution of a screening test (accelerated test) for revealing a potential failure.
Thus, if a defective memory cell is detected at the product test performed subsequent to the stage of the wafer test where a defective memory cell was detected and once relieved by a redundancy circuit, the process of replacing and relieving by the redundancy circuit must be programmed in consideration of the results of the both operation tests. This will require a more complicated analysis for relieving of the defective memory cell.
In particular, the analysis for relieving becomes complicated when a failure is detected again in a memory cell that was once relieved at the product test, after relieving of a defective memory cell detected at the wafer test had been programmed into the redundancy circuit. Thus, if the defective memory cell detected at the product test was once relieved at a row-related redundancy circuit after the wafer test, the defective memory cell must be relieved by a column-related redundancy circuit. On the contrary, if the defective memory cell detected at the product test was once relieved by a column-related redundancy circuit after the wafer test, the defective memory cell must be relieved by a row-related redundancy circuit. In such a case, the analysis for relieving performed after the product test becomes particularly complicated.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device which is configured that a defective memory cell detected by an operation test can be relieved without the need for a complicated analyzing process.
According to an aspect of the present invention, a semiconductor memory device includes a plurality of memory cells; a plurality of redundancy circuits, each of which is used to relieve a defective memory cell that occurred in the plurality of memory cells; and a redundancy control circuit to selectively activate one of the plurality of redundancy circuits when the defective memory cell is designated as an accessing object. The redundancy control circuit includes a first redundancy decoder arranged corresponding to one of the plurality of redundancy circuits and activating the corresponding one redundancy circuit when a defective address stored inside is designated as the accessing object; and a second redundancy decoder arranged corresponding to another one of the plurality of redundancy circuits and activating the corresponding another one redundancy circuit when a defective address stored inside is designated as the accessing object, except for the case where the defective address stored in the first redundancy decoder is designated as the accessing object.
Preferably, when the defective address stored in the first redundancy decoder is designated as the accessing object, the second redundancy decoder inactivates the corresponding another one redundancy circuit, irrespective of whether or not the defective address stored the inside is designated as the accessing object.
Such a semiconductor memory device can execute a replacement and relieving process adapted to the defective address stored in the first redundancy decoder used with a higher priority, without consideration given to the defective address stored in the second redundancy decoder used with a lower priority. Therefore, a final defective memory cell can be replaced and relieved by a redundancy circuit corresponding to the first redundancy decoder (a high-priority decoder) without the need for any consideration given to the defective memory cell detected in the past or the replacement and relieving process corresponding thereto. Thus, a problem can be avoided in that a plurality of memory cell rows or memory cell columns are selected within the same memory array, which may be caused by the problem in the analysis for relieving, without a complicated analyzing process.
REFERENCES:
patent: 5060197 (1991-10-01), Park et al.
patent: 5257229 (1993-10-01), McClure et al.
patent: 5414659 (1995-05-01), Ito
patent: 5485424 (1996-01-01), Kawamura
patent: 5841708 (1998-11-01), Nagata
patent: 2001-35186 (2001-02-01), None
Fujiwara Yoshinori
Yonezu Toshiaki
Le Thong
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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