Semiconductor memory device having redundancy memory cells incor

Details Semiconductor memory device having redundancy memory cells incor Semiconductor memory device having redundancy memory cells incor

1996-11-25

1997-11-11

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 36523002, G11C 700

Patent

active

056871252

ABSTRACT:
In a semiconductor memory device including first and second sub blocks each having a normal memory cell array and at least one redundancy memory cell row, and first and second sub block selecting circuits for selecting the first and second sub blocks, a multiplexer is connected between the first and second sub block selecting circuits and the first and second sub blocks, and redundancy memory cell row exchanging circuits for the redundancy memory cell rows are provided. The multiplexer is controlled in accordance with the output signals of the redundancy memory cell row exchanging circuits and the block selecting circuits, and the selection of the redundancy memory cell rows.

REFERENCES:
patent: 5504712 (1996-04-01), Conan
patent: 5506807 (1996-04-01), Ferrant et al.

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