Semiconductor memory device having redundancy memory cells

Static information storage and retrieval – Read/write circuit – Bad bit

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365201, 3652257, G11C 700

Patent

active

053574702

ABSTRACT:
A semiconductor memory device includes a plurality of memory cell arrays, a plurality of decoders for decoding a first address of memory addresses, each of the decoders being connected to a corresponding memory cell array, and a plurality of sense amplifiers, each connected to a corresponding memory cell array. Also included are a decoder for decoding a second address of the memory addresses, the decoder being connected to every memory cell array, to be shared by every memory cell array, a plurality of redundancy memory cells, each of which is arranged for a corresponding memory cell array, and a plurality of programming circuits, each, arranged relative to a corresponding memory cell array to receive the first memory address and output a signal of a predetermined logic level corresponding to a defective memory cell in a memory cell array. Further, there is included a programmable decoder for receiving the second address and signal from the programming circuits, for changing a decoding state of the second address according to the logic level of the output signal from the programming circuits and for outputting a redundancy memory cell select signal which selects a redundancy memory cell in place of a specified defective memory cell.

REFERENCES:
patent: 4935899 (1990-06-01), Morigami
patent: 5060197 (1991-10-01), Park et al.
patent: 5224073 (1993-06-01), Nakayama
patent: 5243570 (1993-09-01), Saruwatari

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