Semiconductor memory device having redundancy

Details Semiconductor memory device having redundancy Semiconductor memory device having redundancy

1999-11-04

2002-07-23

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230060

Reexamination Certificate

active

06424582

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to synchronous semiconductor memory devices, and more particularly, to a synchronous semiconductor memory device that allows replacement of a defective memory cell by a redundant memory array.
2. Description of the Background Art
Recently, it is general for a semiconductor memory device to include a redundant memory array to repair a partial defect in memory cells by replacing the memory array in the neighborhood of the defective memory cell with a redundant memory array during the manufacturing stage.
In the conventional redundancy system, a memory device includes a row-related redundant memory array and a column-related redundant memory array with a redundancy determination unit corresponding in number to the plurality of redundant memory arrays for setting the replacement address of these redundant memory arrays.
A redundancy determination circuit includes a fuse element and the like used to set the address. This fuse element requires a certain size in order to be reliably burned out by a laser beam or the like. This means that the area on the chip occupied by the redundancy determination circuits becomes greater as more redundant memory arrays are provided.
It is possible to suppress the area occupied by the redundancy determination circuit unit on the chip by using in common the circuit associated with the redundant memory arrays.
FIG. 42
is a first example of a semiconductor memory device including a conventional redundant memory cell disclosed in Japanese Patent Laying-Open No. 2-201800.
When a defective cell is found in a mask ROM cell array
906
in the semiconductor, memory device M (mask ROM) of
FIG. 42
, the address of this defective cell is set at a redundancy determination circuit
903
. Data identical to the data written in that defective cell is applied to a write control circuit
900
, whereby this data is written into a PROM cell array
913
.
When the input address signal matches any redundancy address, a select circuit
915
selects the data output from a second memory unit
914
. This data is output from an output circuit
916
.
By providing a plurality of sets of the second memory unit
914
with respect to the first memory unit
908
, replacement of a plurality of rows or columns can be effected.
FIG. 43
shows a second example of a semiconductor memory device with a conventional redundant memory cell, disclosed in Japanese Patent Laying-Open No. 2-210686.
This second example corresponds to a SRAM.
Consider the case where seven word lines WL and one bit line are defective in a normal cell array
923
in the SRAM of FIG.
43
. In this event, defective word lines WL of normal cell array
923
are repaired by spare word lines RWL
0
-RWL
6
in a redundant memory array
936
. Also, defective bit line BL of normal cell array
923
is repaired by a spare word line RWL
7
. Repair of defective bit line BL with spare word line RWL
7
is carried out by sending the row address that should be applied to a redundant X decoder
935
X to a redundant Y decoder
935
Y.
Thus, both the defective word and bit lines can be repaired with one redundant memory array
936
without having to provide a redundant memory array solely for each of word lines WL and bit lines BL.
FIG. 44
shows a third example of a semiconductor memory device with a conventional redundant memory cell disclosed in Japanese Patent Laying-Open No. 9-162308.
This third example teaches the achievement of repair in the row direction and column direction of the main memory cell with a redundant memory cell provided only in the row direction.
In the event that there is a defective memory cell in a main memory cell array
951
in
FIG. 44
, the row address that selects the row (word line) in which the defective memory cell resides is stored in a row address memory circuit
957
.
It is assumed that four memory cells
941
-
944
connected to a word line WL
2
is replaced with the redundant memory cells. When a memory cell in the row direction is to be repaired, a transistor group AA is at a nonconductive state whereas a transistor group BB is at a conductive state. The data of output signals &phgr;A
1
, &phgr;A
2
, &phgr;B
1
, and &phgr;B
2
selecting word line WL
2
are stored in row address memory circuit
957
. Upon supply of output signals &phgr;A
1
, &phgr;A
2
, &phgr;B
1
and &phgr;B
2
from the row predecoder, row address memory circuit
957
determines whether output signals &phgr;A
1
, &phgr;A
2
, &phgr;B
1
and &phgr;B
2
select word line WL
2
or not.
When the output signal are those that selects word line WL
2
, a disconnect circuit
952
disconnects main memory cell array
951
from a sense amplifier
955
. A redundant memory cell array
953
is activated, whereby the data therein is applied through a column decoder
954
to a sense amplifier
955
. The amplified signal is output outside.
Consider repair of a memory cell in the column direction. It is assumed that four memory cells A-D connected to a column line COL
2
are replaced with redundant memory cells. The data of output signals CA
1
, CA
2
, CB
1
, and CB
2
selecting column line COL
2
are stored in a column address memory circuit
958
. Transistor group AA is set conductive whereas transistor group BB is set nonconductive.
When the output signals are those that select column line COL
2
, disconnect circuit
952
disconnects main memory cell array
951
from sense amplifier
955
. Redundant memory cell array
953
is activated.
The data of the redundant memory cell corresponding to the word line that is activated is sent via column decoder
954
to which signals &phgr;A
1
, &phgr;A
2
, &phgr;B
1
and &phgr;B
2
output from the row predecoder are applied to sense amplifier
955
to be amplified and output.
Thus, repair of a main memory cell in the row direction and the column direction can be achieved with a redundant memory cell provided only in the row direction.
As described above, the approach of using in common a redundant memory cell for the replacement of a defective memory cell in both the word line direction and the bit line direction has been developed.
In the high speed dynamic random access memory (DRAM hereinafter) of great capacity, the memory array is divided into a plurality of banks to render the control more complex. From the standpoint of the operating speed, it is desirable to employ a structure in which a redundant memory array and a regular memory cell use in common a word line/bit line. This is because signal delay of the word line or the bit line does not have to be taken into account.
The defect of a memory cell is mainly attributed to a defective bit line or a defective word line. The possibility of a defective chip that cannot be repaired is high if the redundant memory cell is limited to either the bit line direction or the word line direction.
It is therefore desirable to provide a row-related redundant memory array for row replacement and a column-related redundant memory array for column replacement respectively for each memory bank.
However, the redundancy determination circuit used in fault repair when there is actually a defective location corresponds to only a small portion of one chip. As mentioned before, the redundancy determination circuit provided in each redundant memory array includes a fuse element and the like that occupies a large area for setting the address. Therefore, there was a problem that redundancy determination circuits that are not used occupy a great area on the chip.
At the early stage of development in which the production step is not stable, it is desirable that the DRAM includes a redundancy determination circuit for each redundant memory array so that many redundant memory arrays can be used. In contrast, at the mass production stage, the production step is stabilized so that the frequency of using a redundant memory array becomes lower. It is therefore desirable for the DRAM to have a smaller area for the redundant memory arrays than having many redundant memory arrays from the standpoint of reduc

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