Semiconductor memory device having reduced power...

Details Semiconductor memory device having reduced power... Semiconductor memory device having reduced power...

1999-12-30

2001-04-17

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S226000, C365S230020

Reexamination Certificate

active

06219292

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device which can reduce system power consumed during a refresh operation by performing the refresh operation in a burst method.
2. Description of the Background Art
In general, a dynamic random access memory (DRAM) employs a capacitor as a unit memory device recording a data, which is called a cell. When a data of ‘1’ (or ‘high level’) is stored in the cell, a high potential is applied to the cell, and when a data of ‘0’ ( or ‘low level’) is stored in the cell, a low potential is applied to the cell, thereby recording the data. In an ideal case, the capacitor constituting the cell maintains stored charges, so long as a potential of a connection terminal of the capacitor is not varied. However, actually, as the time elapses, the stored charges are lost as a leakage current. Accordingly, it is impossible to judge whether the recorded data is ‘1’ or ‘0’. In order to constantly maintain the data, a process of periodically sensing and amplifying the data stored in the cell, and restoring it in the cell is necessary. The process is called a refresh operation.
The refresh operation of the DRAM is divided according to a performing method. The RAS only refresh operation consists of a cycle of externally applying a row address strobe signal and a row address on which the refresh operation is performed, raising a word line selected by the row address, amplifying and re-writing the data of the whole cells connected to the word line by a sense amplifier, and dropping the word line. In this case, in order to refresh the whole cells of the DRAM, all the row addresses must be externally inputted.
So as to overcome the aforementioned disadvantage, there has been suggested the auto-refresh operation (or CBR refresh: CAS before RAS refresh). The auto-refresh operation carries out the ‘sensing-amplifying-restoring’ operation, identically to the RAS only refresh operation. However, since the row addresses are sequentially generated inside, it is not necessary to externally input the row addresses. Accordingly, a DRAM user needs not to memorize and input the row addresses on which the refresh operation is performed.
FIG. 1
is a block diagram illustrating a conventional semiconductor memory device performing the auto-refresh operation. As shown therein, the semiconductor memory device includes: a memory cell array
1
consisting of a plurality of memory cells storing data; a command decoder
2
for outputting a refresh command REF controlling the refresh operation according to a chip selection signal/CS, a row address strobe signal/RAS, a column address strobe signal/CAS, and a write enable signal/WE; a timing signal generating unit
3
for outputting a refresh enable signal RASEN for the inside refresh operation according to the output signal REF from the command decoder
1
; a pulse generating unit
4
for generating a pulse signal disabling the refresh enable signal RASEN by using the output signal RASEN from the timing signal generating unit
3
, and supplying it to the timing signal generating unit
3
; a multiplexer
7
for outputting an address externally inputted and buffered by an address buffer
5
during the normal operation, and selectively outputting an internal address outputted by a counter
6
counting the output signal from the command decoder
2
during the refresh operation; and a word line driving unit
8
controlled according to the output signal from the timing signal generating unit
3
, for driving a word line selected by the address which is selectively outputted by the multiplexer
7
.
The timing signal generating unit
3
includes: a first PMOS transistor PM
1
and a first NMOS transistor NM
1
connected in series between the power voltage VCC and the ground voltage VSS, and having their gates connected to receive the output signal from the pulse generating unit
4
and the refresh command REF, respectively; and first and second inverters INV
1
, INV
2
having their outputs and inputs interactively connected to output the refresh enable signal RASEN by inverting and latching a potential of the commonly-connected drain of the first PMOS transistor PM
1
and the first NMOS transistor NM
1
.
The auto-refresh operation of the conventional semiconductor memory device will now be described with reference to an operational timing diagram of FIG.
2
.
Firstly, the command decoder
2
generates the command REF starting the refresh operation from the externally-inputted control signals. That is, the auto-refresh command REF is generated by combining the external chip selection signal/CD, the row address strobe signal/RAS, the column address strobe signal/CAS, and the write enable signal/WE.
For example, in a synchronous DRAM, when the row address strobe signal/RAS is logically low, the column address strobe signal/CAS is logically ‘low’ and the write enable signal/WE is logically ‘high’, the auto-refresh command REF is enabled.
Thereafter, the timing signal generating unit
3
generates the internal refresh signal RASEN by using the auto-refresh command REF outputted from the command decoder
2
. Accordingly, the internal refresh signal RASEN outputted from the timing signal generating unit
3
is applied to the word line driving unit
8
, and controls a signal enabling the word line.
On the other hand, the pulse generating unit
4
generates a precharge signal PCG which is a short pulse in order to automatically perform the precharge operation after a predetermined delay time (until the refresh operation is finished). The precharge signal PCG is a signal for finishing the refresh operation in the synchronous DRAM.
Here, the predetermined delay time is a time when the word line is enabled in the refresh operation, namely a time corresponding to a pulse length tRAS of the row address strobe signal/RAS.
When the conventional semiconductor memory device is normally operated, the address is externally inputted to the address buffer
5
, and supplied to the word line driving unit
8
by the multiplexer
7
, thereby enabling the word line in order to select the selected cell of the memory cell array
1
. In the case that the semiconductor memory device performs the refresh operation, the internal address generated by the counter
6
is supplied to the word line driving unit
8
by the multiplexer
7
, thereby refreshing all the cells in the memory cell array
1
.
In the auto-refresh operation, when the refresh command is inputted once, the refresh operation is carried out one time. However, when the refresh operation needs to be consecutively performed, the refresh signal must be externally consecutively supplied in the structure of FIG.
1
. As a result, the system power is considerably consumed in order to consecutively input the command.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor memory device which can reduce power consumption by consecutively carrying out a refresh operation in a burst method.
In order to achieve the above-described object of the present invention, there is provided a semiconductor memory device including: a memory cell array consisting of a plurality of memory cells storing data; a command decoder for outputting a refresh command controlling a refresh operation according to a chip selection signal, a row address strobe signal, a column address strobe signal, and a write enable signal; a mode register set for programming the number of the refresh operations to be consecutively performed; a burst counter for counting the number of the refresh operation according to the output signal from the mode register set; a first timing signal generating unit for generating an internal refresh enable signal for the inside refresh operation according to the output signal from the command decoder; an internal refresh signal generating unit for outputting a previously-set number of internal refresh signals according to the output signal from the first timing s

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