Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2001-02-02
2002-08-06
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S230030
Reexamination Certificate
active
06430091
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly a semiconductor memory device having a memory cell array of a shared sense amplifier type.
2. Description of the Background Art
In a Dynamic Random Access Memory (DRAM), a boosted potential VPP is used for driving signal lines bearing large loads when reading data from a memory array, and more specifically for driving a word line, a bit w line equalize signal line (BLEQ) and a shared gate signal line (BLI) of a memory cell array of a shared sense amplifier type, which will be described later. Gate circuits which are connected to these signal lines employ N-channel MOS transistors. For transmitting a power supply potential, which is applied to a source of the N-channel MOS transistor, to a drain, it is necessary to apply a H-level, which is higher than the power supply potential by at least an amount corresponding to a threshold voltage, as a gate potential. Therefore, boosted potential VPP is required.
FIG. 17
shows boosted potential VPP which is internally generated.
Referring to
FIG. 17
, boosted potential VPP is generated by a VPP generating circuit arranged within a semiconductor memory device. In VPP generating circuit, an external power supply potential exvdd which is externally supplied to the semiconductor memory device is boosted by a booster circuit such as a charge pump circuit or the like, and thereby boosted potential VPP is generated.
In recent years, however, external power supply potential exvdd has been lowered to increase a potential difference from required boosted potential VPP. Since VPP generating circuit boosts external power supply potential exvdd, which is low, by a charge pump or the like, increase in power consumption at boosted potential VPP requires the charge pump to be formed of transistors having increased sizes. Thereby, the chip area of the semiconductor memory device increases.
In the prior art, therefore, it has been necessary to devise a structure and/or a method for suppressing the power consumption at boosted potential VPP.
FIG. 18
is a circuit diagram showing a structure of a three-state circuit which is used in the prior art for suppressing power consumption at boosted potential VPP.
Referring to
FIG. 18
, this three-state circuit includes a P-channel MOS transistor PQ which is connected between a node receiving boosted potential VPP and an output node NOUT, and receives on its gate a signal A, an N-channel MOS transistor NQ which is connected between output node NOUT and a ground node, and receives on its gate a signal B, and an N-channel MOS transistor NQ
1
which is connected between a node receiving external power supply potential exvdd and output node NOUT, and receives on its gate a control signal C.
For changing the output from 0 V to boosted potential VPP, this three-state circuit operates in such a manner that output node NOUT is boosted from 0 V to external power supply potential exvdd in a first stage, and then the potential on output node NOUT is boosted external power supply potential exvdd to boosted potential VPP in the second stage. In this manner, the power which is consumed at boosted potential VPP generated by VPP generating circuit can be merely equal to that required for boosting the potential from external power supply potential exvdd to boosted potential VPP.
FIG. 19
is an operation waveform diagram showing an operation of the three-state circuit shown in FIG.
18
.
Referring to
FIGS. 18 and 19
, the potential of signal A changes from 0 V to boosted potential VPP at time t
1
, the potential of signal B changes from 0 V to boosted potential VPP and the potential of control signal C changes from external power supply potential exvdd to the ground potential. Thereby, P- and N-channel MOS transistors PQ and NQ
1
are turned off, and N-channel MOS transistor NQ is turned on so that output node NOUT is coupled to the ground node. Therefore, output signal OUT lowers to L-level.
At a time t
2
, the potential of signal B falls from boosted potential VPP to the ground potential, and the potential of control signal C rises from the ground potential to external power supply potential exvdd. Thereby, N-channel MOS transistor NQ is turned off, and N-channel MOS transistor NQ
1
is turned on so that output node NOUT is coupled to external power supply potential exvdd by N-channel MOS transistor NQ
1
. However, the gate potential of N-channel MOS transistor NQ
1
is equal to external power supply potential exvdd. Therefore, voltage drop by an amount equal to threshold voltage Vth occurs. For a period between t
2
and t
3
, therefore, output node NOUT is charged to attain a potential which is lower than external power supply potential exvdd by an amount equal to the threshold voltage.
At a time t
3
, the potential of signal A lowers from boosted potential VPP to L-level. Thereby, P-channel MOS transistor PQ is turned on, and output node NOUT is coupled to boosted potential VPP. Therefore, the potential of signal OUT rises from a value of (exvdd - Vth) to boosted potential VPP after time t
3
. Thereby, the power consumption at boosted potential VPP generated by the VPP generating circuit is merely caused by the boosting after time t
3
.
However, the potential difference between boosted potential VPP and external power supply potential exvdd has been considerably increased in accordance with lowering of the external power supply potential. Therefore, the potential on the output node is raised by a large amount after time t
3
so that the effect of reducing the power consumption at boosted potential VPP has been reduced.
For increasing the effect of reducing the power consumption while preventing the potential from lowering by the magnitude corresponding to threshold voltage Vth, the potential of control signal C at H-level can be equal to boosted potential VPP. In this case, however, P- and N-channel MOS transistors PQ and NQ
1
couple boosted potential VPP to external power supply potential exvdd when output node NOUT is coupled to boosted potential VPP by P-channel MOS transistor PQ. Thereby, leak from boosted potential VPP to external power supply potential exvdd occurs.
SUMMARY OF THE INVENTION
An object of the invention is to provide a semiconductor memory device, in which power consumption at boosted potential VPP is reduced so that sizes of transistors contained in a VPP generating circuit and therefore a chip area can be small.
In summary, the invention provides a semiconductor memory device including a memory cell array, a voltage generating circuit, a first internal node, a first control circuit and a first drive circuit.
The memory cell array includes a plurality of memory cells arranged in rows and columns for storing externally applied data. The voltage generating circuit receives and boosts an externally applied first power supply potential to generate a second power supply potential to be used for data transmission with respect to the memory cell array. The first internal node is activated by the second power supply potential. The first control circuit issues first and second control signals for driving the first internal node in accordance with an externally applied input signal. The first control circuit activates the first control signal for a predetermined time in accordance with change in the input signal, and activates the second control signal upon elapsing of the predetermined time after the change in the input signal. The first drive circuit receives the first and second power supply potentials, and drives the potential on the first internal node to the second power supply potential in accordance with the first and second control signals. The first drive circuit includes a first switch circuit to be turned on to couple the first power supply potential to the first internal node in accordance with the first control signal, and a second switch circuit to be turned on to couple the second power supply potential to the first internal node in accordance with the second contr
Le Vu A.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Phung Anh
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