Semiconductor memory device having reading operation of informat

Details Semiconductor memory device having reading operation of informat Semiconductor memory device having reading operation of informat

1989-02-14

1991-06-04

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Differential sensing

365185, 36518909, G11C 702, G11C 1140

Patent

active

050220098

ABSTRACT:
First and second bit lines are arranged on one side of each sense amplifier while third and fourth bit lines are arranged on the other side thereof. A first dummy cell is connected to either the first bit line or the second bit line. In addition, a second dummy cell is connected to either the third bit line or the fourth bit line. When a memory cell connected to the first bit line is selected, the second dummy cell is simultaneously selected. On this occasion, the first bit line is connected to a first terminal of the sense amplifier, and the third bit line and the fourth bit line are connected to a second terminal of the sense amplifier. Potentials of the first and second terminals are differentially amplified. On the other hand, when a memory cell connected to the third bit line is selected, the first dummy cell is simultaneously selected. On this occasion, the third bit line is connected to the second terminal of the sense amplifier, and the first bit line and the second bit line are connected to the first terminal of the sense amplifier. The potentials of the first and second terminals are differentially amplified.

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patent: 4677590 (1987-06-01), Arakawa
patent: 4694427 (1987-09-01), Miyamoto et al.
patent: 4805143 (1989-02-01), Matsumoto et al.
patent: 4819212 (1989-04-01), Nakai et al.
IEEE Journal of Solid-State Circuit-vol. SC-15, No. 5, Oct. 1980, pp. 831-839.
Dumitru Cioaca et al., "A Million-Cycle CMOS 256K EEPROM", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 684-692.
Fujio Masuoka et al., "A 256-Kbit Flash E.sup.2 PROM Using Triple-Polysilicon Technology", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 4, Aug. 1987, pp. 548-552.
Masanobu Yoshida et al., "An 80 ns Address-Date Multiplex 1 Mb CMOS EPROM", IEEE International Solid-State Circuits Conference, Feb. 25, 1987, pp. 70, 71 and 342.

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