Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
1999-02-04
2001-02-27
Zarabian, A. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S185250, C365S203000
Reexamination Certificate
active
06195297
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device including read-only memory (ROM) cells, and more particularly to the improvement of the read operation speed thereof.
2. Description of the Related Art
A prior art semiconductor memory device is constructed by a memory cell array including a plurality of ROM cells connected to a plurality of bit lines, a plurality of sense amplifiers each including a MOS transistor connected to one of the bit lines, a reference volatage generating circuit for applying a reference voltage to a gate of the MOS transistor, and a bit line selection circuit for generating a plurality of bit line selection signals for selecting the respective bit lines.
In the above-described prior art ROM device, however, the reference voltage may be decreased due to the capacitive coupling of the gate and source (drain) of the MOS transistor. As a result, the speed of the read operation is decreased. This will be explained later in detail
SUMMARY OF THE INVENTION
It is an object of the present invention to suppress the reduction of the speed of the read operation of a semiconductor memory device including ROM cells.
According to the present invention, in a semiconductor memory device constructed by a memory cell array including a plurality of ROM cells connected to a plurality of bit lines, a plurality of sense amplifiers each including a first MOS transistor connected to one of the bit lines, a reference voltage generating circuit for applying a reference voltage to a gate of the first MOS transistor, and a bit line selection circuit for generating a plurality of bit line selection signals for selecting the bit lines respectively, a plurality of second MOS transistors, each of which is connected between one of the bit lines and the ground terminal, is provided. Also, a plurality of inverters are connected between the bit line selection circuit and the second MOS transistors, so that the second MOS transistors are controlled by inverted signals of the bit line selection signals.
Thus, only one selected bit line is precharged while the other non-selected bit lines are decreased to ground or remain at ground.
REFERENCES:
patent: 5835432 (1998-11-01), Nakano
patent: 61-144793 (1986-07-01), None
patent: 7-29373 (1995-01-01), None
patent: 7-111085 (1995-04-01), None
patent: 7-240093 (1995-09-01), None
patent: 7-307091 (1995-11-01), None
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
Zarabian A.
LandOfFree
Semiconductor memory device having pull-down function for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device having pull-down function for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having pull-down function for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2561015