Semiconductor memory device having preamplifier with...

Details Semiconductor memory device having preamplifier with... Semiconductor memory device having preamplifier with...

2002-10-16

2004-03-30

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S189050, C365S208000, C365S233100

Reexamination Certificate

active

06714471

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device operating at high frequencies in synchronization with a rise and a fall of an external clock and including a preamplifier amplifying data read from a memory cell array to be output to a data bus pair.
2. Description of the Background Art
By demand for a higher frequency operation of a semiconductor device, a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) allowing data input/output in synchronization with a rising edge and a falling edge of an external clock has been developed and brought into practical use.
FIG. 10
is a timing chart showing a data output timing in reading data from a DDR SDRAM that is a so-called DDR-I. In this DDR SDRAM, a CAS latency CL is set at 2.0 and a burst length BL is set at four. Here, CAS latency represents the number of cycles (one cycle corresponds to the rise of an external clock CLK to the next rise) required for DDR SDRAM to receive an READ command (a command for reading data) from the outside and then to start to output the read data to the outside. Furthermore, the burst length represents the number of bits successively read in response to READ command.
Referring to
FIG. 10
, DDR-I outputs data DQ that is the read data and a data strobe signal DQS in synchronization with external clocks CLK, /CLK. Here, external clock /CLK is a clock signal complimentary to external clock CLK. Data strobe signal DQS is a signal for use as a take-in timing of data DQ at an external controller receiving data DQ.
A timing difference tAC between the edges of external clocks CLK, /CLK and the output of data DQ is defined to fall within a certain range. In
FIG. 10
, timing difference tAC is controlled at zero.
In order to realize a data output as shown in
FIG. 10
, there is need for an operation clock of which timing is slightly earlier than the timing of the edges of external clocks CLK, /CLK at a data output circuit. This is because a delay occurs from an input of the external clock to the semiconductor memory device to an actual output of data due to the capacity of each circuit which is included in the device.
More specifically, what is required is a clock generation circuit operated in a manner as follows. As external clocks CLK, /CLK are fixed-cycle signals, internal clocks CLK_P, CLK_N shifted backward by an appropriate time Ta with respect to the edges of external clocks CLK, /CLK are generated by delaying external clocks CLK, /CLK by an appropriate delay amount Td. Furthermore, the delay amount Td can be controlled such that data DQ output from the data output circuit operating using these internal clocks CLK_P, CLK_N as a trigger and data strobe signal DQS output from a data strobe signal output circuit satisfy the aforementioned timing difference tAC. A circuit generating such an internal clock is called a DLL (Delay Locked Loop) circuit.
Now, in order to carry out the data output as shown in
FIG. 10
, a so-called pipeline operation is necessary in which data read from the memory cell array is appropriately shifted in synchronization with internal clocks CLK_P, CLK_N and is finally delivered to an output buffer. More specifically, the data read from the memory cell array sequentially passes through each stage forming a pipeline at an appropriate timing synchronized with internal clocks CLK_P, CLK_N and reaches the output buffer. Although a variety of configurations may be employed as a stage configuration of the pipeline, a first stage may correspond to a segment up until the read data is output to a data bus pair DB and /DB after a preamplifier.
FIG. 11
is a functional block diagram functionally illustrating the circuit configuration from a bit line pair BL and /BL to data bus pair DB and /DB in a case where the segment described above is a first stage of the pipeline.
Referring to
FIG. 11
, a sense amplifier
50
detects and amplifies data read from the memory cell array (not shown) onto bit line pair BL and /BL. Thereafter, a decode signal YA corresponding to an externally received column address goes to H (logic high) level. After an appropriate delay time period, a column decode enable signal CDE for activating a column select line CSL goes to H level. Accordingly, the output of an AND gate
108
goes to H level and one column select line CSL corresponding to the column address is selected. Then data is output at small amplitude from sense amplifier
50
through N-channel MOS transistors N
1
, N
2
onto an I/O line pair LIO and /LIO. It is noted that an I/O equalizer
102
is a circuit equalizing I/O line pair LIO and /LIO at H level in advance before data is output onto I/O line pair LIO and /LIO. Then, the data on I/O line pair LIO and /LIO is input to a preamplifier
148
.
Preamplifier
148
includes an amplifier circuit
222
, a latency shifter
124
and a driver
126
. Here, latency shifter
124
configures a data shift circuit.
Amplifier circuit
222
resets the internal state based on a signal PACL output from a delay circuit
104
and amplifies a small amplitude signal on I/O line pair LIO and /LIO by a differential amplifier included therein based on a signal PAEL output from a delay circuit
106
. Amplifier circuit
222
then outputs the amplified signal onto data line pair PD
3
and /PD
3
.
Latency shifter
124
holds data received from data line pair PD
3
and /PD
3
until a signal RDT goes to H level, and outputs the data onto data line pair PDD and /PDD at a timing when signal RDT goes to H level. Driver
126
outputs data received from data line pair PDD and /PDD onto data bus pair DB and /DB at small amplitude.
Here, signal RDT received by latency shifter
124
is a signal that determines the timing at which data is moved from a first stage to a second stage in the pipeline operation, and determines the timing at which the data amplified by amplifier circuit
222
is output onto data bus pair DB and /DB. Signal RDT is generated by a control circuit (not shown), starting from a clock cycle following a clock cycle that is a starting point of reading corresponding data from the memory cell array.
Delay circuit
104
receives column decode enable signal CDE and outputs signal PACL produced by delaying column decode enable signal CDE by an appropriate amount to delay circuit
106
and to amplifier circuit
222
in preamplifier
148
. This signal PACL provides a timing for resetting the internal state in preamplifier
148
. Delay circuit
106
receives signal PACL output from delay circuit
104
and outputs signal PAEL produced by delaying signal PACL by an appropriate amount to amplifier circuit
222
. This signal PAEL provides a timing for amplifying the signal received from I/O line pair LIO and /LIO in amplifier circuit
222
in preamplifier
148
for output to latency shifter
124
.
FIGS. 12-16
are circuit diagrams showing a circuit configuration of amplifier circuit
222
. Amplifier circuit
222
includes an input processing circuit
132
, a PAE generation circuit
234
, a CLRES generation circuit
136
, a /PAEC generation circuit
138
and an amplify/output circuit
240
.
Referring to
FIG. 12
, input processing circuit
132
includes an inverter
1322
, an NAND gate
1324
and an NOR gate
1326
. A signal /PAEQ generated in response to signal PACL output from delay circuit
104
is a signal for equalizing differential amp nodes PAN, /PAN in amplify/output circuit
240
described later. Signal PADT generated in response to signal PAEL output from delay circuit
106
is a signal being at H level from H level of signal PACL to H level of signal PAEL, for connecting differential amp nodes PAN and /PAN to I/O line pair LIO and /LIO to take in data on I/O line pair LIO and /LIO into preamplifier
148
, in amplify/output circuit
240
described later.
Referring to
FIG. 13
, PAE generation circuit
234
includes inverters
2342
-
2346
. Signals PAE, /PAE generated in response to signal PAEL are signals for activating a differential ampli

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