Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2002-12-27
2004-09-14
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S233100, C365S189050
Reexamination Certificate
active
06791888
ABSTRACT:
This application claims the priority of Korean Patent Application No. 2002-29110, filed May 25, 2002, the entire contents of which are hereby incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a preamble function.
2. Description of the Related Art
Data output from a semiconductor memory device having a preamble function, such as dual data rate synchronous dynamic random access memory (DDR SDRAM), is output after the preamble section ends.
FIG. 1
is a timing diagram of a conventional semiconductor memory device having a preamble function. Referring to
FIG. 1
, when a read command (READ) is in synchronization with an external clock signal (ECLK) and an input to a semiconductor memory device (notshown), a latency control signal (Latencyds) is in synchronization with an internal clock signal (DLL CLK). Moreover, the latency control signal (Latencyds) is activated under such conditions. During the activation of the latency control signal (Latencyds), an output data strobe signal (DQS) output from the semiconductor memory device is changed from a logic high level to a logic low level. As a result, output data (DQ) has a preamble section tp. The preamble section tp is maintained for one cycle of the internal clock signal (DLL CLK), and the output data strobe signal (DQS) is activated and output external to the semiconductor memory device when a latency signal (Latency) is activated.
As described above, according to the conventional semiconductor memory device, the preamble section tp is maintained only for one cycle of the internal clock signal (DLL CLK). Therefore, it is possible to maintain the preamble section tp when the operational frequency of the semiconductor memory device is low. However, if the operational frequency of the semiconductor memory device is high, e.g., the operational frequency is more than 300 MHz, the duty cycle of the internal clock signal (DLL CLK) becomes very short. In this case, a starting point of the preamble section tp may be delayed or the preamble section tp may not be present, which prevents the semiconductor memory device from stably outputting data.
In conclusion, the higher the operational frequency of a semiconductor memory device, the more difficult it is to maintain a preamble section tp.
SUMMARY OF THE INVENTION
An exemplary embodiment of the present invention provides a semiconductor memory device in which a preamble section is sufficiently secured.
An exemplary embodiment of the present invention provides a semiconductor memory device having a preamble function, including an output driver for generating a data strobe signal and, outputting the same external to the semiconductor memory device. The embodiment also includes a preamble unit for preambling the data strobe signal by changing an output signal of the output driver from a high impedance status to a logic low level. This is achieved in synchronization with an activation of a read command input to the semiconductor memory device.
In addition, an exemplary embodiment of the present invention provides a semiconductor memory device having a preamble function, including a data controller for generating a data signal in response to data generated at an internal circuit of the semiconductor memory device when a latency signal, which sets the latency of the semiconductor memory device, is activated. The semiconductor memory device may also include an output driver for generating a data strobe signal in response to the data signal, a preamble controller for outputting a preamble control signal in response to a read command input to the semiconductor memory device, and a preamble unit for preambling the data strobe signal by changing an output signal of the output driver from a high impedance status to a logic low level, when the preamble control signal is activated.
Furthermore, an exemplary embodiment of the present invention provides a semiconductor memory device having a preamble function, including an output driver having a pull-up unit for generating a data strobe signal in response to a data signal and a control signal generated at an internal circuit of the semiconductor memory device. The pull-up unit is activated to output the data strobe signal to a logic high level when the data signal is at a logic low level. Furthermore, the pull-down unit is activated to output the data strobe signal to a logic low signal when the control signal is at a logic high level. The semiconductor memory device may further include a logic unit for outputting the control signal to a logic high level and sending the same to the pull-down unit when at least one of the data signal and the preamble control signal generated in response to a read command input to the semiconductor memory device is at a logic high level. According to an exemplary embodiment of the present invention, an output of the output driver is maintained at a high impedance status during a stand-by state, the pull-down unit is activated when the preamble control signal becomes active, and then, the output of the output driver is changed from the high impedance status to a logic low level; therefore, the data strobe signal output from the semiconductor memory device is preambled.
Still further, an exemplary embodiment of the present invention provides a semiconductor memory device having a preamble function. The semiconductor memory device includes a data controller for outputting a data signal in response to data generated at an internal circuit of the semiconductor memory device. The foregoing occurs when a latency signal, which sets the latency of the semiconductor memory device, is activated. The semiconductor device further includes an output driver for generating an output data strobe signal, a pull-up unit being activated to output the data strobe signal to a logic high level when the data signal output from the data controller is at a logic low level, and a pull-down unit being activated to output the data strobe signal to a logic low level when the input control signal is at a logic high level. Furthermore, the device includes a preamble controller for outputting a preamble control signal in response to a read command input to the semiconductor memory device, and a logic unit for outputting an output signal to a logic high and inputting the same to the pull-down unit when at least one of the preamble control signal and the data signal is at a logic high level. The logic unit is for preambling the data strobe signal by changing the data strobe signal to a logic low level when the preamble control signal is activated.
An exemplary embodiment of the present invention provides a semiconductor memory device having a preamble function. The semiconductor device includes an output driver for outputting a data strobe signal to the outside of the semiconductor memory device, and a preamble unit for receiving a read command in synchronization with a clock of an external clock signal input to the semiconductor memory device and outputting a control signal. The output driver also may output a control signal to change the data strobe signal from a high impedance status to a logic low level in response to the control signal in synchronization with the clock of the external clock signal.
Furthermore, an exemplary embodiment of the present invention provides a semiconductor memory device having a preamble function. The device includes a data controller for generating a data signal in response to data generated at an internal circuit of the semiconductor memory device when a latency signal, which sets the latency of the semiconductor memory device, is activated. Furthermore, the semiconductor device includes an output driver for outputting a data strobe signal in response to the data signal, a preamble controller for receiving a read command in synchronization with a clock of an external clock signal input to the semiconductor memory device and outputting a preamble control
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