Semiconductor memory device having plural memory mats with centr

Details Semiconductor memory device having plural memory mats with centr Semiconductor memory device having plural memory mats with centr

1994-05-27

1997-03-25

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Bad bit

365 63, 365 69, 365190, 36523003, 36523006, G11C 2900

Patent

active

056151560

ABSTRACT:
A semiconductor memory device having reserve bit lines or word lines for replacing defective bit lines or word lines which can increase a defect relief probability and improve an operational margin. The reserve bit lines or word lines are provided approximately in a central portion of a memory mat. Because of a low probability of defect occurrence in the reserve word lines or bit lines, the probability of defect occurrence can be made low when a defective word line or bit line is replaced with a reserve word line or bit line.

REFERENCES:
patent: 4847810 (1989-07-01), Tagani
patent: 5134588 (1992-07-01), Kubota et al.
patent: 5214601 (1993-05-01), Hidaka et al.
patent: 5355337 (1994-10-01), Kim
patent: 5394369 (1995-02-01), Kagami

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