Semiconductor memory device having plural biasing circuits for s

Details Semiconductor memory device having plural biasing circuits for s Semiconductor memory device having plural biasing circuits for s

1989-08-10

1991-06-04

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

365226, 3072962, G11C 700

Patent

active

050220055

ABSTRACT:
A dynamic random access memory device according to the present invention has a plurality of memory cells each of the one-transistor and one-capacitor type and a plurality of biasing circuits for injecting electrons into the semiconductor substrate so as to establish a predetermined reverse biasing state, and the biasing circuits are located in spacing relationship from one another, so that a large difference in electron density does not take place in the substrate, and, accordingly, a data bit in the form of positive electric charges is less liable to be destroyed even if the storage capacitor is located in the vicinity of the biasing circuits.

REFERENCES:
patent: 4535423 (1985-08-01), Nozaki et al.
patent: 4760560 (1988-07-01), Ariizumi et al.

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