Semiconductor memory device having parallel test mode for...

Details Semiconductor memory device having parallel test mode for... Semiconductor memory device having parallel test mode for...

2000-04-19

2001-06-05

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S063000, C365S230030

Reexamination Certificate

active

06243309

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device; and, more particularly, to a semiconductor memory device having a parallel test mode for simultaneously testing a plurality of memory cells.
DESCRIPTION OF THE PRIOR ART
Referring to
FIG. 1
, there is shown a block diagram illustrating a conventional dynamic random access memory (DRAM) device. As shown, the conventional DRAM device includes a memory cell array
100
, sense amplifiers
200
a
to
200
d
, a data latch circuit
300
, a data output driver
400
and a buffer
500
. The memory cell array
100
includes memory cell blocks
100
a
to
100
d
. The memory cell blocks
100
a
to
100
d
include a plurality of memory cells (not shown), respectively.
A pair of data lines is coupled between one memory cell block and one sense amplifier, wherein one data line is complementary to the other data line. That is, a pair of two complementary data lines D
0
and D
0
Z is coupled between the memory cell block
100
a
and the sense amplifier
200
a
. A pair of two complementary data lines D
1
and D
1
Z is coupled between the memory cell block
100
b
and the sense amplifier
200
b
. A pair of two complementary data lines D
2
and D
2
Z is coupled between the memory cell block
100
c
and the sense amplifier
200
c
. A pair of two complementary data lines D
3
and D
3
Z is coupled between the memory cell block
100
d
and the sense amplifier
200
d
. The memory cell block
100
a
or
100
d
, to be selected for the sake of testing, transfers stored complementary data signals to the sense amplifier
200
a
or
200
d
. The corresponding sense amplifier
200
a
or
200
d
amplifies the complementary data signals. The sense amplifiers
200
a
to
200
d
transfer the amplified complementary data signals to global data bus lines GRIO and GRIOZ. The global data bus lines GRIO and GRIOZ are coupled between the sense amplifiers
200
a
to
200
d
and the data latch circuit
300
. The data latch circuit
300
latches the amplified complementary data signals. The data latch circuit
300
sends the latched amplified complementary data signals to lines PU and PD. The lines PU and PD are coupled between the data latch circuit
300
and the data output driver
400
. Lines A and B are coupled between the data output driver
400
and the buffer
500
. The buffer
500
buffers data signals sent from the data output driver
400
and sends the buffered data signals to a data output pin. The buffer
500
includes PMOS and NMOS transistors.
TABLE 1
Cell
Data Output
State
Data
D0
D0Z
GRIO
GRIOZ
PU
PD
A
B
Pin
Read
Low
Low
High
High
Low
Low
High
High
High
Low
High
High
Low
Low
High
High
Low
Low
Low
High
As shown in Table 1, if a memory cell (not shown) of the memory cell block
100
a
is selected and stores a logic low signal as cell data, the complementary data lines D
0
and D
0
Z convey logic low and high signals, respectively. At this time, the global data bus lines GRIO and GRIOZ convey the logic high and low signals amplified by the sense amplifier
200
a
, respectively. Then, the buffer
500
output the logic low signal conveyed through the data latch circuit
300
and data output driver
400
to the data output pin.
Further, as shown in Table 1, if the complementary data lines D
0
and D
0
Z convey the logic high and low signals, respectively, the buffer
500
outputs the logic high signal to the data output pin.
TABLE 2
Data
State
D0
D0Z
GRIO
GRIOZ
PU
PD
A
B
Output Pin
High
High
High
High
High
Low
Low
High
Low
Hi-Z
Impedance
As shown in Table 2, if the conventional DRAM device is in a high impedance (Hi-Z) state, the complementary data lines D
0
and D
0
Z convey the logic high signals, respectively. Further, the global data bus lines GRIO and GRIOZ convey the logic high signals, respectively. As shown in Table 2, the data output pin has a Hi-Z signal having a level between the logic high and low signals.
Since the conventional DRAM device has a pair of global data bus lines as described above, only one memory cell contained in a memory cell block selected can be tested at a time. Accordingly, in order to simultaneously test each memory cell contained in the memory cell blocks, the conventional DRAM device needs additional global data bus lines and an additional circuit.
Referring to
FIG. 2
, there is shown a block diagram depicting a conventional semiconductor memory device having a parallel test mode, which simultaneously tests each memory cell contained in four memory cell blocks. As compared with the conventional DRAM device shown in
FIG. 1
, the conventional semiconductor memory device having the parallel test mode further includes a logical operation circuit
600
as a data compression circuit. The conventional DRAM device includes a pair of global data bus lines, while the conventional semiconductor memory device having the parallel test mode includes four pairs of global data bus lines.
A sense amplifier
200
a
amplifies complementary data signals received from a memory cell block
100
a
through complementary data lines D
0
and D
0
Z. Global data bus lines GRIO
1
and GRIO
1
Z convey the complementary data signals amplified by the sense amplifier
200
a
. Similarly, a sense amplifier
200
d
amplifies complementary data signals received from a memory cell block
100
d
through complimentary data lines D
3
and D
3
Z.
Global data bus lines GRIO
0
and GRIO
0
Z, GRIO
1
and GRIO
1
Z, GRIO
2
and GRIO
2
Z, and GRIO
3
and GRIO
3
Z convey the complementary data signals amplified by the sense amplifiers
200
b
to
200
d
, respectively. The four pairs of global data bus lines are coupled to the logical operation circuit
600
.
The logical operation circuit
600
receives four pairs of the amplified complementary data signals from four pairs of global data bus lines coupled to the logical operation circuit
600
. After receiving the four pairs of the amplified complementary data signals, the logical operation circuit
600
carries out a logical operation with respect to the four pairs of the amplified complementary data signals. After carrying out the logical operation with respect to the four pairs of the amplified complementary data signals from the global data bus lines GRIO
0
and GRIO
0
Z, GRIO
1
and GRIO
1
Z, GRIO
2
and GRIO
2
Z, and GRIO
3
and GRIO
3
Z, the logical operation circuit
600
outputs a pair of logical operation signals through lines CU and CD.
A data latch circuit
300
latches the pair of logical operation signals and outputs the latched logical operation signals to a data output driver
400
. A buffer
500
buffers data signals outputted from the data output driver
400
, thereby generating a test pass or fail signal.
TABLE 3
Line
Data
Line
Data
Line
Data
Line
Data
Line
Data
Pin
Data
D0
Low
GRIO0
High
CU
High
PU
Low
A
High
Data
Low
D1
Low
GRIO1
High
output
D2
Low
GRIO2
High
pin
D3
Low
GRIO3
High
D0Z
High
GRIO0Z
Low
CD
Low
PD
High
B
High
D1Z
High
GRIO1Z
Low
D2Z
High
GRIO2Z
Low
D3Z
High
GRIO3Z
Low
As shown in Table 3, when the conventional semiconductor memory device having the parallel test mode simultaneously tests each memory cell contained in the four memory cell blocks to which a logic low signal has been written, the conventional semiconductor memory device generates the test pass signal, i.e., the logic low signal.
TABLE 4
Line
Data
Line
Data
Line
Data
Line
Data
Line
Data
Pin
Data
D0
High
GRIO0
Low
CU
Low
PU
High
A
Low
Data
High
D1
High
GRIO1
Low
output
D2
High
GRIO2
Low
pin
D3
High
GRIO3
Low
D0Z
Low
GRIO0Z
High
CD
High
PD
Low
B
Low
D1Z
Low
GRIO1Z
High
D2Z
Low
GRIO2Z
High
D3Z
Low
GRIO3Z
High
As shown in Table 4, when the conventional semiconductor memory device having the parallel test mode simultaneously tests each memory cell contained in the four memory cell blocks to which a logic high signal has been written, the conventional semiconductor memory device generates the test pass signal, i.e., the logic high signal.
TABLE 5
Line
Data
Line
Data
Line
Data
Line
Data
Line
Data
Pin
Data
D0
High
GRIO0
Low
CU
Low
PU
Low
A
High
Data
Hi-Z
D1
High
GRIO1
Low
output
D2
Low
GRIO2
High
pi

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