Semiconductor memory device having overdriven bit-line sense...

Details Semiconductor memory device having overdriven bit-line sense... Semiconductor memory device having overdriven bit-line sense...

2003-02-05

2004-06-22

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S204000

Reexamination Certificate

active

06754122

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-028559, filed Feb. 5, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to correction of a potential to which bit lines are equalized when a overdriving method is used in the memory core section to improve the reading speed of bit line sense amplifiers. For example, the present invention is applied to memory integrated circuit, logic-merged semiconductor memories, etc.
2. Description of the Related Art
With dynamic random access memories (DRAMs), readout, amplification and restoration of small-signal data from memory cells are performed by bit-line sense amplifiers. Japanese Unexamined Patent Publication 2002-25264 discloses a DRAM which, in order to improve the reading speed of bit line sense amplifiers, adopts an overdrive system to drive the sense amplifiers with a voltage (overdriving voltage) higher than a restore potential at the beginning of cell data amplification, thereby effecting high-speed data amplification.
With the DRAM disclosed in the above publication, an overdrive potential higher than the restore potential is applied to a P-type sense amplifier at the initial stage of cell data readout, thereby performing the overdriving operation. Overdriving results in the timing of sensing the bit line potential being advanced. After that, overdriving is stopped and a restore potential is applied to the bit line charged up to the overdriving potential, so that the bit line potential is stabilized at the restore potential. Subsequently, the bit line pair is precharged to a precharge potential and then equalized.
With increasing speed of DRAMs, shortening the active period to increase the reading speed results in the period for stabilizing the bit line at the restore potential being shortened. As a result, the bit line potential after the potential on the bit line charged to a high potential by overdriving and the potential on the bit line charged to a low potential have been equalized is affected by an increase in potential resulting from the overdriving operation. For this reason, the bit line potential after equalization will be higher than an intermediate value between the restore potentials of the paired bit lines.
The potential on a bit line of the equalized bit line pair is used as reference potential in reading cell data in the next cycle. For this reason, reading cell data in the state where the potential on the equalized bit line pair has been increased as a result of an increase in potential resulting from overdriving results in the reduced margin for reading “1” data. It therefore becomes difficult to read cell data correctly. Therefore, the demand has increased for solving this problem.
BRIEF SUMMARY OF THE INVENTION
According to the present invention, there is provided a semiconductor memory device comprises: a plurality of memory cells; a plurality of bit line pairs connected to the memory cells; a plurality of bit line sense amplifiers each of which is connected to a corresponding one of the bit line pairs to amplify the potential difference across the corresponding bit line pair; an overdrive potential generating circuit which generates an overdrive potential; a first sense amplifier driver connected between each of the bit line sense amplifiers and the overdrive potential generating circuit to output the overdrive potential to the bit line amplifiers; a second sense amplifier driver connected between each of the bit line amplifiers and a predetermined potential to output the predetermined potential to the bit line amplifiers; a plurality of bit line precharge/equalization circuits each of which is connected to a corresponding one of the bit line pairs and a precharge potential line to precharge each of the bit line pairs with the precharge potential and equalize the potentials on each of the bit line pairs; and at least one discharge circuit coupled to the bit line pairs to discharge the potentials on the bit line pairs to a discharge potential.


REFERENCES:
patent: 6115316 (2000-09-01), Mori et al.
patent: 6347058 (2002-02-01), Houghton et al.
patent: 6477100 (2002-11-01), Takemura et al.
patent: 6487133 (2002-11-01), Wada et al.

Affiliated with

Also associated with

Rating

Semiconductor memory device having overdriven bit-line sense... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having overdriven bit-line sense..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having overdriven bit-line sense... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3297078