Semiconductor memory device having optimum refresh cycle...

Details Semiconductor memory device having optimum refresh cycle... Semiconductor memory device having optimum refresh cycle...

2006-07-11

2006-07-11

Yoha, Connie C. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S211000, C365S212000, C365S233100, C327S512000, C327S513000

Reexamination Certificate

active

07075847

ABSTRACT:
An apparatus for controlling a refresh cycle in a semiconductor memory device includes a temperature detection controller for generating a detection control signal and a converting control signal; a temperature detection block, which is enabled by the detection control signal, for generating an analog detection voltage in response to a temperature variation; an analog to digital converter, which is enabled by the converting control signal, for converting the analog detection voltage into a digital control code; and a refresh controller for generating a refresh cycle control signal based on the digital control code in order to control the refresh cycle.

REFERENCES:
patent: 6453218 (2002-09-01), Vergis
patent: 6556496 (2003-04-01), Benedix et al.
patent: 6809978 (2004-10-01), Alexander et al.
patent: 06-162759 (1994-06-01), None
patent: 100200723 (1999-03-01), None

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