Semiconductor memory device having on-chip test circuit and oper

Details Semiconductor memory device having on-chip test circuit and oper Semiconductor memory device having on-chip test circuit and oper

1990-05-23

1992-07-21

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Testing

3652335, G11C 700, G11C 2900

Patent

active

051329379

ABSTRACT:
Same test data is written into corresponding memory cells of each subarray of a memory cell array to be read out. A comparing and determining circuit determines whether the data read out from each memory cell has the same logic or not, and the data proves defective when any one of the data has different logic. An output of the comparing and determining circuit is stored in a register to be externally outputted through a predetermined pin (e.g. output enable pin). Timing in which the register accepts the data stored in the comparing and determining circuit is controlled by a switching controlling signal generating circuit disposed in a semiconductor memory device. As the above, all signals necessary for a test are generated in the semiconductor memory device, and the test result is outputted through an existing pin, so that it is structured by the same number of pins as that of a standard semiconductor memory device without a testing function.

REFERENCES:
patent: 4541090 (1985-09-01), Shiragasawa
patent: 4549101 (1985-10-01), Sood
patent: 4752929 (1988-06-01), Kantz et al.
patent: 4768194 (1988-08-01), Fuchs
patent: 4833652 (1989-05-01), Isobe et al.
patent: 4849973 (1989-07-01), Kubota
patent: 4860259 (1989-08-01), Tobita
patent: 4868823 (1989-09-01), White, Jr. et al.
patent: 4897817 (1990-01-01), Katanosaka
patent: 4899313 (1990-02-01), Kumanoya et al.
patent: 4956819 (1990-09-01), Hoffmann et al.
Pinaki Mazumder, "Parallel Testing of Parametric Faults in a Three-Dimensional Dynamic Random-Access Memory", Aug. 1988, IEEE Journal of Solid-State Circuits, vol. 23, No. 4, pp. 933-940.

Affiliated with

Also associated with

Rating

Semiconductor memory device having on-chip test circuit and oper does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having on-chip test circuit and oper, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having on-chip test circuit and oper will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-850025