Semiconductor memory device having nonvolatile memory cell...

Details Semiconductor memory device having nonvolatile memory cell... Semiconductor memory device having nonvolatile memory cell...

2002-08-23

2004-04-06

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

Reexamination Certificate

active

06717841

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a configuration of a memory cell of a static random access memory (SRAM).
2. Description of the Background Art
Random access memories (RAMs) which are memory devices capable of arbitrarily writing, holding and reading data are mainly divided into a dynamic RAM (DRAM: Dynamic Random Access Memory) which requires a refresh operation to hold stored data and a static RAM (SRAM: Static Random Access Memory) which does not require a refresh operation.
SRAM is characterized in that although the structure thereof is more complicated than DRAM and cost per unit capacity is high than that of DRAM, high rate data read and write operations can be performed because of no need to perform a refresh operation. Due to this, SRAM is employed as, for example, a cache memory or the like which requires following up the rate of a high rate CPU (Central Processing Unit). Recently, in particular, SRAM is widely used for a portable terminal equipment or the like which operates by a battery with relatively low power consumption.
FIG. 5
is a circuit diagram showing one example of the configuration of an SRAM memory cell. In
FIG. 5
, a so-called CMOS (Complementary Metal Oxide Semiconductor) memory cell which consists of six MOS transistors is shown.
Referring to
FIG. 5
, pMOS transistors PT
1
and PT
2
and nMOS transistors NT
1
and NT
2
form two CMOS inverters to hold the signal levels of storage nodes N
1
and N
2
and a CMOS flip-flop circuit is constituted by cross-coupling the two CMOS inverters. To write and read data to and from storage nodes N
1
and N
2
, access transistors NT
3
and NT
4
are turned on in response to the activation of a word line WL (to H level), whereby storage nodes N
1
and N
2
are electrically connected to bit lines BL and /BL, respectively.
If word line WL is deactivated (to L level) and access transistors NT
3
and NT
4
are turned off, either nMOS transistor or the pMOS transistor is turned on in each CMOS inverter in accordance with the level of the data stored in corresponding storage node N
1
or N
2
. As a result, one of storage nodes N
1
and N
2
is connected to one of a power supply voltage VCC corresponding to the “H” level of the data and a ground voltage GND corresponding to the “L” level of the data and the other storage node is connected to the other voltage VCC or GND in accordance with the level of the data held in the memory cell. It is, therefore, possible to hold the data in the memory cell in a stand-by state without periodically turning on word line WL and executing a refresh operation.
FIG. 6
is a circuit diagram showing one example of another configuration of an SRAM memory cell. In
FIG. 6
, a so-called p-type TFT (Thin Film Transistor) load type memory cell which consists of four MOS transistors and two p-type thin film transistors PPT
1
and PPT
2
is shown. Thin film transistors PPT
1
and PPT
2
indicate transistors of a conductive type P each formed out of a polysilicon thin film.
Referring to
FIG. 6
, nMOS transistors NT
1
and NT
2
hold the signal levels of storage nodes N
1
and N
2
, respectively. Thin film transistors PPT
1
and PPT
2
are connected in parallel between power supply voltage VCC and storage node N
1
and node N
2
, respectively. It is noted that nMOS transistors NT
1
and NT
2
will be also referred to as “driver transistors”. Thin film transistors PPT
1
and PPT
2
and nMOS transistors NT
1
and NT
2
constitute a flip-flop circuit. To write and read data to and from storage nodes N
1
and N
2
, access transistors NT
3
and NT
4
are turned on in response to the activation of word line WL (to H level), whereby storage nodes N
1
and N
2
are electrically connected to bit lines BL and /BL, respectively. The data write and read operations of the p-type TFT load SRAM memory cell are the same as those of the CMOS memory cell stated above. A multilayer structure can be adopted as the cell structure of this p-type TFT load SRAM memory cell. That is, it is possible to form thin film transistors PPT
1
and PPT
2
on a different layer from that of driver transistors NT
1
and NT
2
on a semiconductor substrate. Therefore, p-type TFT load SRAM memory cell has an advantage in that a cell area is small.
FIG. 7
is a circuit diagram showing one example of yet another configuration of an SRAM memory cell. In
FIG. 7
, a so-called high resistance load memory cell which consists of four MOS transistors and two high resistances R
1
and R
2
is shown.
Referring to
FIG. 7
, this high resistance load memory cell differs from the memory cell shown in
FIG. 6
in that thin film transistors PPT
1
and PPT
2
are replaced by high resistances R
1
and R
2
, respectively. It is noted that high resistances R
1
and R
2
and driver transistors NT
1
and NT
2
constitute a so-called high resistance load type flip-flop circuit. The other operations and the like of the high resistance load memory cell are the same as those of the CMOS memory cell stated above. A multilayer structure can be adopted as the cell structure of this high resistance load memory cell as in the case of the p-type TFT load memory cell. That is, it is possible to form high resistances R
1
and R
2
on a different layer from that of driver transistors NT
1
and NT
2
on a semiconductor substrate and to make the cell area small.
As one of the indicators for the operating stability of an SRAM memory cell, a static noise margin is employed.
FIG. 8
is a conceptual view showing the relationship of the static noise margin when the CMOS memory cell is in a stand-by state. As shown in
FIG. 8
, the input/output characteristic of the CMOS memory cell is indicated by the characteristic view of two cross-coupled inverters.
In case of
FIG. 8
, the characteristic curve k
1
of one CMOS inverter is given. By inverting characteristic curve k
1
symmetrically about a line, indicated by a dotted line in
FIG. 8
, having 45 degrees with respect to vertical and horizontal axes, a characteristic curve k
2
is obtained. This characteristic curve k
2
corresponds to the characteristic curve of the other CMOS inverter cross-coupled to one CMOS inverter stated above. A combination of characteristic curves k
1
and k
2
corresponds to the input/output characteristic view of the CMOS memory cell. In this case, as shown in
FIG. 8
, a region surrounded by curves k
1
and k
2
and normally referred to as “cell's eye” is formed. The maximum distance L
1
between curves k
1
and k
2
in the region corresponds to a static noise margin. It is indicated that if the distance is larger, the input/output characteristic of the CMOS memory cell is more stable.
Points S
1
and S
2
shown in
FIG. 8
are stable points. Stable point S
1
corresponds to a state in which data “0” is stored. Stable point S
2
corresponds to a state in which data “1” is stored. In addition, a point S
3
is a metastable point. Even if the operation of the CMOS memory cell corresponds to point S
3
in an initial state, it never fails to be moved to either point S
1
or S
2
whenever microscopic noise occurs and is stabilized at the moved point.
On the other hand, the input/output characteristic view of the CMOS memory cell when data is read from the cell changes as shown in FIG.
9
. As already stated above, when data is read from the memory cell, access transistors NT
3
and NT
4
are both turned on and storage nodes N
1
and N
2
are electrically connected to bit lines BL and /BL, respectively. As a result, the so-called cell's eye, i.e., the static noise margin becomes very narrow during data read as shown in FIG.
9
. If the so-called cell's eye disappears, it is difficult to hold the data.
It is said that the area of above-stated p type TFT load memory cell can be made smaller than that of the CMOS memory cell, which area is about eight times as large as that of a DRAM memory cell if manufactured under the same design standard (design rule). This is because the p type th

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