Semiconductor memory device having non-selecting level generatio

Details Semiconductor memory device having non-selecting level generatio Semiconductor memory device having non-selecting level generatio

1995-03-10

1996-02-13

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Semiconductive

365205, 365207, 36518909, 36518905, G11C 700

Patent

active

054916550

ABSTRACT:
A semiconductor memory device has a plurality of memory cells arranged in rows and columns, a plurality of pairs of complementary first and second bit lines arranged corresponding to respective columns and connecting memory cells on a corresponding column, first and second read data lines, and a plurality of pairs of first and second bipolar transistor provided for respective pairs of first and second bit lines. Each first bipolar transistor is coupled to the first read data line and each second bipolar transistor is coupled to the second read data line and a plurality of first switching circuits transfer potentials of the first and second bit lines to respective bases of corresponding first and second bipolar transistors. A reference line transmits a non-selection level voltage and a plurality of second switching circuits, operating complementary to the corresponding first switching circuits, transfer the non-selection level voltage to bases of corresponding first and second bipolar transistors. Generator circuitry generates non-selection level voltage having (i) a potential level lower than or equal to a low level potential of a selected bit line in a data reading operation mode and (ii) a potential level higher than or equal to a high level potential of the selected bit line in an operation mode other than the data reading operation mode.

REFERENCES:
patent: 4939693 (1990-07-01), Tran
patent: 4982372 (1991-01-01), Matsuo
patent: 5239507 (1993-08-01), Ohba
patent: 5392243 (1995-02-01), Nakamura
"A 12-NS ECL I/O 256KX1-Bit SRAM Using A 1.mu.MBICMOStechnology", Robert Kertis et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988.
"An 8-NS 256K ECL SRAM with CMOS Memory Array and Battery Backup Capability", Hiep Van Tran et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988.
"A 7-NS 1-MB BICMOS ECL SRAM with Shift Redundancy", Atsushi Ohba et al., IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991.

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