Semiconductor memory device having N-channel MOS transistor for

Details Semiconductor memory device having N-channel MOS transistor for Semiconductor memory device having N-channel MOS transistor for

1998-08-03

1999-11-30

Nelms, David

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

36523003, G11C 700

Patent

active

059954329

ABSTRACT:
In a semiconductor memory device including a plurality of memory cells connected between sub word lines and bit lines, a plurality of sub word line driver columns for driving the sub word lines, and a plurality of sense amplifier columns for sensing voltages at the bit lines, a plurality of sense amplifier control circuits are provided at cross areas between the sub word line driver columns and the sense amplifier columns. A first sense amplifier control circuit is constructed by a CMOS circuit forming an interface between global input/output lines and local input/output lines. A second sense amplifier control circuit is constructed by an N-channel MOS circuit forming a pull down circuit for pulling down NMOS sources of flip-flops of the sense amplifier columns and a first pull up circuit for pulling up PMOS sources of the flip-flops of said sense amplifier columns. A third sense amplifier control circuit is constructed by a P-channel MOS circuit forming a second pull up circuit for pulling up the PMOS sources of the flip-flops of the sense amplifier columns.

REFERENCES:
patent: 5831924 (1998-11-01), Nitta et al.
patent: 5835436 (1998-11-01), Ooishi
patent: 5875149 (1999-02-01), Oh et al.
M. Nakamura et al., "A 29-ns 64-Mb DRAM with Hierarchical Array Architecture", pp. 1302-1307, IEEE Journal of Solid-State Circuits, vol. 31, No. 9, Sep. 1996.

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