Semiconductor memory device having multilevel memory cell...

Details Semiconductor memory device having multilevel memory cell... Semiconductor memory device having multilevel memory cell...

1998-09-28

2002-11-12

Fahmy, Wael (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S391000, C365S189070, C365S185030, C365S185200

Reexamination Certificate

active

06479874

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a multilevel mask ROM (Read Only Memory) of an ion implantation type in which each memory cell stores multilevel data.
2. Description of the Prior Art
A mask ROM is also called a fixed ROM, and by using a mask including user data upon a wafer fabrication process, the mask ROM is manufactured having the data stored therein. In the mask ROM, individual data are stored in memory cells each composed of a piece of cell transistor. Formerly, the memory cell was arranged to store binary data “0” or “1” according to a state of whether a bit line was connected or not connected to the cell transistor. However, recently, the technique in which the threshold voltage V
th
of each the cell transistor generally made of a MOS (Metal-Oxide-Semiconductor) FET (Field Effect Transistor) is adjusted by using such as an ion implantation technique to make each cell transistor store adjusted binary data, thereby increasing a storage capacity of a mask ROM. In case of the mask ROM which stores data by changing the threshold voltage V
th
in this way, a reference cell of the same structure as the memory cell which stores data is provided in the ROM in advance, and a reference current to be obtained from the reference cell and a current which flows in the memory cell at a read time are compared to reproduce the binary data.
Moreover, for the purpose of further increasing the storage capacity, a technique has been developed lately in which a plurality of bit data can be stored in each memory cell by making each memory cell store one of the multilevel data of three or more levels. A mask ROM in which each memory cell is arranged to store multilevel data of three or more levels in this way is called a multilevel mask ROM.
In the multilevel mask ROM, the threshold voltage V
th
of the cell transistor of each memory cell is changed by ion implantation according to multilevel data to be stored in the memory cell. If the write data to be input to each memory cell is the data of N-level, a threshold voltage corresponding to the write data is selected from among threshold voltages of N kinds and set in the cell transistor of the memory cell. In this multilevel mask ROM, N−1 pieces of reference cells having different threshold voltages are provided beforehand. The structure of the reference cell is identical to that of the memory cell, and a current which flows in the memory cell at the read time and a reference current to be obtained from each reference cell are compared to reproduce the multilevel data. The reference current is compared as a criterion for distinguishing data with a current which flows when the cell transistor of the memory cell is switched on with its threshold voltage.
For example, if it is assumed that N=4, threshold voltages for the cell transistor of the memory cell are V
t0
to V
t3
, and V
t0
<V
t1
<V
t2
<V
t3
, then the threshold voltages of the cell transistors of the reference cells are set to the same threshold voltages V
t0
to V
12
, respectively, as those of the cell transistors of the memory cells. The reference current is set by providing a predetermined offset by means of such as a known offset circuit so that th e reference current becomes approximately an intermediate value of each current which flows whe n the memory cell is switched on with each threshold voltage.
Since the predetermined data is stored by changing the threshold voltage of the cell transistor made of a MOSFET through an ion implantation process , the ion implantation process is also called code ion implantation process.
FIG. 1
is a block diagram showing the general structure of a multilevel mask ROM. Here, the multilevel mask ROM is a 4-level mask ROM in which each memory cell stores one of 4-level data.
The multilevel mask ROM comprises memory cell
21
for storing data, sense amplifier
22
for reading data from memory cell
21
, a first, second and third reference cells
23
a
to
23
c
to be used as criteria against memory cell
21
, a first, second and third reference amplifiers
24
a
to
24
c
for producing reference currents by using reference cells
23
a
to
23
c
, respectively, comparison circuit
25
for discriminating data stored in memory cell
21
by comparing the output of sense amplifier
22
and the output of each of reference amplifiers
24
a
to
24
c
, and logic synthesis circuit
26
for outputting 2-bit data through logic synthesis of the output result of comparison circuit
25
. Here, the reference current is the current which serves as the criterion for distinguishing data stored in memory cell
21
. In
FIG. 1
, although there is illustrated only one memory cell
21
, a plurality of memory cells are actually disposed as a memory cell array, and by receiving an address from the outside, a memory cell corresponding to the address is selected. As a result, sense amplifier
22
reads the data from the selected memory cell to output it to comparison circuit
25
.
Memory cell
21
and reference cells
23
a
to
23
c
each has a cell transistor made of a MOSFET, having the same structure. The threshold voltage of the cell transistor can be set to a desired value by changing the amount of ion to be injected to a channel region provided directly under the gate o f the cell transistor. Now, since the 4-level mask ROM is taken into consideration, memory cell
21
is set to any one of threshold voltages of V
t0
, V
t1
, V
t2
and V
t3
(where V
t0
<V
t1
<V
t2
<V
t3
) corresponding to its data stored. In order to distinguish these data of 4-level, the threshold voltages of cell transistors of a first, second and third reference cells
23
a
to
23
c
are set to V
t0
, V
t1
and V
t2
, respectively.
Further, with reference to a first, second and third reference amplifiers
24
a
to
24
c
, prescribed offsets are provided respectively so that the respective reference currents become approximately the mean value of the currents which flow when the cell transistor of memory cell
21
is switched on with respective threshold voltages. Here, V
t0
is the threshold voltage of the cell transistor when no ions are injected to the channel region directly under the gate.
In the 4-level mask ROM of a like structure, for reproducing the data, the output of sense amplifier
22
and the output of the first reference amplifier
24
a
are first compared by comparison circuit
25
. At this time, if the output of sense amplifier
22
is smaller than the output of the first reference amplifier
24
a
, it is determined that the threshold voltage of the corresponding memory cell
21
is V
t0
. Then, comparison circuit
25
compares the output of sense amplifier
22
and the output of the second reference amplifier
24
b
, and when the output of sense amplifier
22
is between the output of the first reference amplifier
24
a
and the output of the second reference amplifier
24
b
, the threshold voltage of that memory cell
21
is determined as V
t1
, Next, comparison circuit
25
compares the output of sense amplifier
22
and the output of the third reference amplifier
24
c
, and when the output of sense amplifier
22
is between the output of the second reference amplifier
24
b
and the output of the third reference amplifier
24
c
, the threshold voltage of that memory cell
21
is determined as V
t2
. When the output of sense amplifier
22
is larger than the output of the third reference amplifier
24
c
, the threshold voltage of that memory cell
21
is determined as V
t3
. By distinguishing the respective threshold voltages of memory cell
21
in this way, data stored in memory cell
21
can be reproduced. Here, description has been made with reference to the successive comparison made by comparison circuit
25
between the output of sense amplifier
22
and the output of each of reference amplifiers
24
a
to
24
c
, however, of course it is possible to prepare a circuit which allows parallel comparison.
By the way, in the semiconduc

Affiliated with

Also associated with

Rating

Semiconductor memory device having multilevel memory cell... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having multilevel memory cell..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having multilevel memory cell... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2967794