Semiconductor memory device having multibit data bus and...

Details Semiconductor memory device having multibit data bus and... Semiconductor memory device having multibit data bus and...

2000-08-28

2002-07-09

Hoang, Huan (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S189050, C365S230080

Reexamination Certificate

active

06418066

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices and in particular to dynamic semiconductor memory devices.
2. Description of the Background Art
In recent years, semiconductor memory devices have data bus configurations which are effective in reduction of wiring delay to achieve faster operation.
FIG. 25
is a conceptual view showing a hierarchical data bus. This configuration has been introduced by Kiyoo Ito in
Ultra LSI Memory
, Baihukan, pp. 168-169.
The semiconductor memory device shown in
FIG. 25
has memory blocks #0 to #k−1 arranged adjacently and having columns selected by a common column decoder and driver. A column selected in each memory block is connected to a respectively associated local data bus.
In
FIG. 25
, a column selected in memory block #k−1 is connected to a local data bus I/O
1
which is connected to a main data bus I/O
2
. Then a main amplifier MA
1
amplifies the data which is in turn transmitted to a global data bus I/O
3
and further transmitted by a main amplifier MA
2
externally.
This configuration is characterized in that by dividing a local data bus the load capacity of a data bus to be driven by a sense amplifier provided in a block can be reduced to accommodate faster operation without increasing the load driving capability of the sense amplifier provided in the block.
A semiconductor memory device is also adapted to replace a defective memory cell existing therein with a spare memory cell to equivalently repair the defective memory cell and thus improve product yield. In a redundant circuit configuration provided with a spare memory cell (spare word and bit lines) for such repair of a defective memory cell, to improve the utilization efficiency of a spare line (a word line or bit line) and that of a spare decoder for selecting the spare line, a flexible redundancy technique has been proposed (see, e.g., Horiguchi et al., “A Flexible Redundancy Technique for High-Density DRAM's”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26 NO.1, JANUARY, 1991, pp. 12-17).
FIG. 26
schematically shows the entire configuration of a semiconductor memory device in a conventional, flexible redundancy configuration.
Referring to
FIG. 26
, the semiconductor memory device includes four memory arrays MA
0
-MA
3
. In each of memory arrays MA
0
-MA
3
, a spare word line is arranged for repairing a defective memory cell row. Spare word lines SW
00
and SW
01
, SW
10
and SW
11
, SW
20
and SW
21
, and SW
30
and SW
31
are arranged in memory arrays MA
0
, MA
1
, MA
2
and MA
3
, respectively.
Respectively associated with memory arrays MA
0
-MA
3
, row decoders X
0
-X
3
are arranged for driving to selected state a normal word line corresponding to an addressed row.
A column decoder Y
0
for decoding a column address signal and selecting an addressed column is arranged between memory arrays MA
0
and MA
1
, and a column decoder Y
1
is arranged between memory arrays MA
2
and MA
3
.
The semiconductor memory device also includes spare decoders SD
0
-SD
3
for storing a row address having a defective memory cell and holding a word line corresponding to the defective row address (or a defective normal word line) in non-selected state and driving a corresponding spare word line to selected state when the defective row address is addressed, and an OR circuit G
0
receiving a signal output from spare decoders SD
0
and SD
1
and an OR circuit G
1
receiving a signal output from spare decoders SD
2
and SD
3
.
A signal output from OR circuits G
0
and G
1
is supplied commonly to spare word line drive circuits included respectively in row decoders X
0
to X
3
. Spare decoders SD
0
-SD
3
receive common array address signal bits an-
2
and an-
1
addressing one of memory arrays MA to MA
3
and common in-array address signal bits a
0
to an-
3
addressing a row in a memory array.
When array address signal bits an-
2
and an-
1
are supplied and a memory array corresponding thereto is addressed, one of row decoders X
0
-X
3
that is associated with the addressed memory array is activated. OR circuits G
0
and G
1
are associated with the two spare word lines, respectively, provided in each of memory arrays MA
0
-MA
3
.
For example, if memory array MA
0
has defective normal word lines W
0
and W
1
, memory array MA
1
has a defective normal word line W
2
and memory array MA
2
has a defective normal word line W
3
, then the address of normal word line W
0
is programmed in spare decoder SD
0
, the address of normal word line W
1
is programmed in spare decoder SD
2
, the address of normal word line W
2
is programmed in spare decoder SD
3
and the address of normal word line W
3
is programmed in spare decoder SD
1
.
A signal output from OR circuit G
0
designates any of spare word lines SW
00
, SW
10
, SW
20
and SW
30
, and a signal output from OR circuit G
1
selects any of spare word lines SW
01
, SW
11
, SW
21
and SW
31
.
When normal word line W
0
is designated, a signal output from spare decoder SD
0
is driven to selected state and a signal output from OR circuit G
0
is activated. In this state, array address signal bits an-
2
and an-
1
activates row decoder X
0
and the remaining row decoders X
1
-X
3
are held inactive.
Thus the word line drive circuit included in row decoder X
0
drives spare word line SW
00
to selected state in response to the signal output from OR circuit G
0
, while a decode circuit provided in row decoder X
0
and associated with normal word line W
0
is held inactive. Thus, defective normal word line W
0
is substituted by spare word line SW
00
.
Similarly, defective normal word lines W
1
, W
2
and W
3
are substituted by spare word lines SW
01
, SW
11
and SW
20
, respectively.
In the flexible redundancy configuration shown in
FIG. 26
, one spare word line can be activated by any of a plurality of spare decoders. For example, spare word line SW
20
can be driven to selected state by spare decoder SD
0
or SD
1
.
Furthermore, one spare decoder can drive any of a plurality of spare word lines to selected state. For example, spare decoder SD
0
can drive any of spare word lines SW
00
, SW
10
, SW
20
and SW
30
to selected state.
Thus the correspondence between spare word line and spare decoder is not one to one and this can enhance the utilization efficiency of spare word line and spare decoder.
More specifically, a spare decoder can be shared by memory arrays to eliminate the necessary of providing a spare decoder for each spare word line and thus reduce chip occupied area.
With such a data bus configuration as the hierarchical data bus configuration described above, substituting a defective normal column with a spare column requires considering how a spare column be arranged, since a local data bus is divided within one memory block.
In such an embedded application as incorporating a semiconductor memory device into a semiconductor device as one block, using a multibit data bus to transfer data allows faster operation and the number of data buses is thus increased. When the number of data buses is increased, consideration must be taken of how a spare column be arranged.
In the flexible redundancy configuration described above, a defective row is repaired through substitution using a spare word line arranged in a memory array including the defective row. Thus, each memory array is disadvantageously required to have a spare word line arranged therein and this degrades the utilization efficiency of the spare word line. Substituting a defective normal word line of a memory array with a spare word line of another memory array to improve the utilization efficiency of the spare word line is not taken into consideration at all, since such substitution would entail complicated control of the circuitry associated with the memory arrays and is thus considered to be avoided.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device with a multibit data bus, having a redundant circuit configuration advantage

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