Semiconductor memory device having minimal leakage current

Details Semiconductor memory device having minimal leakage current Semiconductor memory device having minimal leakage current

1996-10-31

1998-05-05

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Capacitors

365205, 365206, 327 51, G11C 1124

Patent

active

057485208

ABSTRACT:
Precharge circuits precharge plural pairs of bit lines to a specified potential when no word line is selected (during standby). Pull-down transistors are turned ON when the corresponding word lines are not selected so as to connect the corresponding word lines to a common power source line, which is connected to the ground. In a path connecting the above common power source line to the ground is disposed an impedance changing means for changing the impedance of the path between a value during standby and another value during operation during which any word line is selected so that the value during standby is set higher than the value during operation. Consequently, during standby, a leakage current (standby current) resulting from a short circuit between a bit line and a word line is reduced.

REFERENCES:
patent: 5508965 (1996-04-01), Nomura et al.
"Latching-Node Clock Design in Half-VDD Bit-Line CMOS Sense Amplifier", IBM Technical Disclosure Bulletin, vol. 28, No. 4, pp. 1716-1718, Sep. 1985.

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