Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-04-19
2004-01-27
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S209000, C257S211000, C257S208000, C257S774000, C257S210000, C257S306000, C257S307000, C257S308000, C438S238000, C438S239000, C438S386000, C438S399000
Reexamination Certificate
active
06683339
ABSTRACT:
BACKGROUND OF THE INVENTION
This application claims the benefit of Korean Patent Application No. 2000-66171, filed on Nov. 8, 2000, under 35 U.S.C. §119, the contents of which are herein incorporated by reference in their entirety.
1. Technical Field
The present invention generally relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a metal contact structure and a method of manufacturing the same.
2. Discussion of Related Art
In semiconductor memory devices such as dynamic random access memory (DRAM) devices, a metal contact serves to connect a metal line with various components including, for example, an active area, a gate electrode, a bit line, and an upper electrode of a capacitor. The metal contact is usually disposed on a periphery region of the semiconductor memory device.
The basic memory cell of a dynamic RAM device, which includes a single transistor and a capacitor is small and a very dense array can be made using these cells. The major cost of a semiconductor memory is usually the cost of the silicon wafer, thus, the more chips on a wafer, the lower cost per chip. Dynamic RAMs therefore have a lower cost per bit than memories with less compact arrays.
FIG. 1
is a cross-sectional view illustrating a conventional semiconductor memory device having a metal contact structure. As shown in
FIG. 1
, the memory device includes a cell region
100
and a periphery region
200
. In the cell region
100
, a gate electrode
14
is disposed on an active area
12
of a silicon substrate
10
. The silicon substrate
10
and an active area
12
are integrally formed, and protruding portions of the substrate
10
are used as the active area (i.e., a channel area)
12
. Bit lines
16
and a capacitor C are formed over the gate electrode
14
. The capacitor C includes upper and lower electrodes
17
and
18
. A first metal contact
26
a
is disposed to contact a metal line
28
with the upper electrode
17
of the capacitor C.
In the periphery region
200
, bit line contacts
24
are disposed to respectively connect the bit lines
16
with the active area
12
and the gate electrode
14
. Second metal contact
26
b
and third metal contact
26
c
are formed in metal contact holes that are each between adjacent bit lines
16
, to connect the metal line
28
with the active area
12
and the gate electrode
14
, respectively. Also, a fourth metal contact
26
d
connects the metal line
28
with the bit line
16
. First insulating layer
20
and second insulating layer
22
electrically insulate the components described above from each other, and are preferably made of an oxide such as, for example, SiOx.
The metal contacts
26
are usually formed after forming the upper electrode
17
of the capacitor C. At this time, the metal contacts should precisely be aligned with the active area
12
, the gate electrode
14
, and the bit lines
16
, which have already been formed. Since the alignment margin is relatively large in the areas where the first metal contact
26
a
connects the metal lines
28
with the upper electrode
17
of the capacitor C, and where the fourth metal contact
26
d
connects the metal line
28
with the bit line
16
, a very precise alignment is not required. On the other hand, the second metal contact
26
b
and third metal contact
26
c
each require a very precise alignment with the active area
12
, the gate electrode
14
, and the bit lines
16
. As a chip size becomes smaller, the second and third metal contacts
26
b
and
26
c
disposed on the periphery region
200
have an increasingly narrow alignment margin with the active area
12
, the gate electrode
14
, and the bit lines
16
. Therefore, the semiconductor manufacturing process, especially the photolithography process, becomes more difficult.
FIG. 2
is an enlarged view illustrating a portion D of FIG.
1
. The metal line
28
disposed on the periphery region
200
is connected with the active area
12
and the gate electrode
14
via the second and third metal contacts
26
b
and
26
c
, respectively. As described above, the second and third metal contacts
26
b
and
26
c
should each be disposed between two adjacent bit lines
16
. As a chip size becomes smaller, an alignment margin thus becomes reduced; therefore, a short circuit between the metal contacts
26
b
and
26
c
and the neighboring bit line
16
is more likely to occur due to a misalignment.
In efforts to try to overcome the problem described above, a metal contact stud technique may be used.
FIGS. 3 and 4
are exemplary cross-sectional views illustrating a conventional semiconductor memory device having a metal contact structure using a metal contact stud. As shown in
FIG. 3
, metal contact studs
27
a
and
27
b
connect upper and lower portions
26
b
1
and
26
b
2
of the second metal contact
26
b
, and upper and lower portions
26
c
1
, and
26
c
2
of the third metal contact
26
c
, respectively. The metal contact studs
27
a
and
27
b
are formed at the same time as the bit lines
16
following the formation of the lower portions
26
b
2
and
26
c
2
of the second and third metal contacts
26
b
and
26
c
, respectively. After forming the metal contact studs
27
a
and
27
b
, the upper portions
26
b
, and
26
c
1
of the second and third metal contacts
26
b
and
26
c
are connected, respectively, with the lower portions
26
b
2
and
26
c
2
of the second and third metal contacts
26
b
and
26
c
via the metal contact studs
27
a
and
27
b
. As a result, an alignment margin is increased.
However, as shown in
FIG. 4
, as a chip size becomes smaller, a gap between the adjacent two bit lines
16
becomes increasingly narrow; it thus becomes very difficult to secure sufficient space to dispose the metal contact stud
27
. This results in a very difficult manufacturing process and a low manufacturing yield.
Accordingly, a need exists for a semiconductor memory having a metal contact structure that can secure sufficient space to dispose the metal contact stud, and which has an improved manufacturing process and a high manufacturing yield.
SUMMARY OF THE INVENTION
According to an aspect of the present invention, a semiconductor memory device is provided having bit lines and a metal contact stud, wherein the metal contact stud is formed on a different layer from a layer on which the bit lines are formed.
Preferably, the metal contact studs are formed under the bit lines. In addition, a lower portion of the metal contact stud is preferably smaller in area than an upper portion thereof.
In one aspect of the present invention, a semiconductor memory device is provided comprising: a metal contact formed in between adjacent bit lines, said metal contact having an upper portion and a lower portion thereof; and a metal contact stud for connecting said upper portion to the lower portion, wherein the metal contact stud is formed on a different layer from a layer on which the bit lines are formed.
In another aspect of the present invention, a method of manufacturing a semiconductor device is provided comprising the steps of: a) forming gate electrodes on a substrate having a cell region and a periphery region; b) forming a first insulating layer over the substrate, the first insulating layer covering the gate electrodes; c) forming first metal contact holes and stud holes in the first insulating layer; d) forming metal contact studs and first metal contact portions in the stud holes and the first metal contact holes, respectively; e) forming a second insulating layer on the first insulating layer and on the metal contact studs; f) forming bit line contact holes passing through the first and second insulating layers; g) forming bit line contacts in the bit line contact holes; and h) forming bit lines on the second insulating layer.
Advantageously, since the metal contact studs of the present invention are formed on the different layer from the layer on which the bit lines are formed, an alignment margin to form the metal contacts is increased. Therefore, for example, a short circuit
F. Chau & Associates LLP
Im Junghwa
Samsung Electronics Co. LTD
Thomas Tom
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