Semiconductor memory device having memory transistors with...

Details Semiconductor memory device having memory transistors with... Semiconductor memory device having memory transistors with...

2000-03-14

2003-12-02

Nguyen, Cuong Quang (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000

Reexamination Certificate

active

06657251

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-067823, filed Mar. 15, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and, more particularly, to a memory cell array structure of a nonvolatile semiconductor memory which has memory transistors with gate electrodes of a double-layer stacked structure and a method of fabricating the same. Those semiconductor memory device and method are adapted to a NAND type EEPROM (Electrically Erasable and Programmable ROM).
A conventional method of fabricating memory cells will be described below referring to
FIGS. 1A through 1G
.
A gate oxide film
101
of SiO
2
is formed 8 nm thick on the flat-finished major surface of a substrate
100
of, for example, p type silicon, and a first conductive polycrystalline silicon film
102
is formed 100 nm thick on this gate oxide film
101
. Then is formed a silicon nitride film (SiN)
103
with a thickness of 150 nm as an etching mask to remove the first polycrystalline silicon film
102
(FIG.
1
A).
Next, a photoresist is coated on the entire surface of the silicon nitride film
103
and is then processed by photolithography, thus forming a resist pattern
104
. With the resist pattern
104
as a mask, the silicon nitride film
103
is patterned to be an etching mask by anisotropic dry etching such as RIE (Reactive Ion Etching) (FIG.
1
B).
Then, the resist pattern
104
is removed by wet etching. Next, with the patterned silicon nitride film
103
used as a mask, the first polycrystalline silicon film
102
, the gate oxide film
101
and the semiconductor substrate
100
are selectively etched to a desired depth by anisotropic dry etching. This forms trenches
105
that surround device regions (FIG.
1
C).
Then, a post-RIE oxide film
106
is formed 10 nm thick in order to recover from the damages on the etched side of the gate oxide film
101
and the etched surface of the semiconductor substrate
100
(FIG.
1
D).
Next, a buried insulating film
107
of SiO
2
or the like is formed 600 nm thick on the entire surface of the semiconductor substrate
100
to bury the trenches
105
between the first polycrystalline silicon film
102
. The buried insulating film
107
is then planarized to the desired height by CMP (Chemical Mechanical Polishing), thus exposing the silicon nitride film
103
(FIG.
1
E).
Thereafter, the silicon nitride film
103
is removed by wet etching, forming device isolation regions comprising the buried insulating film
107
(FIG.
1
F).
Then, an ONO film (SiO
2
—SiN—SiO
2
)
108
is deposited 12 nm thick on the entire surfaces of the first polycrystalline silicon film
102
and the buried insulating film
107
. Thereafter, a second polycrystalline silicon film
109
and a high-melting-point or refractory metal silicide film
110
of Ti, W or the like are deposited in order on this ONO film
108
(FIG.
1
G).
Thereafter, to form word lines (WL), the refractory metal silicide film
110
, the second polycrystalline silicon film
109
, the ONO film
108
and the first polycrystalline silicon film
102
are processed in order by anisotropic dry etching. Then, ion implantation is carried out to form source/drain regions in the semiconductor substrate
100
by which memory cells are completed.
In the case where a memory cell array whose electrodes have such a double-layer stacked structure is adapted to a nonvolatile semiconductor memory (e.g., EEPROM), if the post-RIE oxide film
106
is a thermal oxide film, the gate size varies depending on the oxidation rate. That is, as the oxidation rate of the first polycrystalline silicon film
102
is fast with respect to the semiconductor substrate
100
, the edge portions of the electrodes are cut back from (come inside) the edge portions of the device regions (FIG.
1
G).
In general, an EEPROM has a floating gate electrically isolated from the peripheral sections and stores data of “1” or “0” by injecting or discharging electrons into or from the floating gate. When a high electric field of about 10 MV/cm is applied to both ends of the silicon oxide film, a tunnel current of the order of 10
−10
A/&mgr;m
2
flows. This current is called FN (Fowler-Nordheim) current.
Injection of electrons (writing) is implemented by applying a high voltage of 20V to a control gate (CG) and setting the source/drain region of the semiconductor substrate to 0V as shown in FIG.
2
A. Under this situation, a floating gate (FG) has a high potential and a high electric field is applied to the gate oxide film, so that the FN current flows to the source/drain region from the floating gate (FG). As electrons travel in the opposite direction to that of the current, electrons are injected into the floating gate (FG).
In discharging (erasing) electrons from the floating gate (FG), as shown in
FIG. 2B
, 0V is applied to the control gate (CG) and 20V to the drain region. Under this situation, a high electric field is generated toward the floating gate (FG) from the drain region. As a result, the FN current flows to the floating gate (FG) from the drain region and electrons are discharged from the floating gate (FG).
As shown in
FIG. 2C
, a strong electric field is applied to the gate oxide film at the portion where the end portion of the floating gate on which the electric field concentrates in this operation faces the source/drain region, thereby damaging the gate oxide film.
Even in the write operation of the nonvolatile memory in
FIG. 1G
, electrons are injected into the first polycrystalline silicon film
102
, so that the voltage of about 20V applied to the refractory metal silicide film
110
produces the FN current in the gate oxide film
101
.
To discharge electrons from the first polycrystalline silicon film
102
in the erasing operation of the nonvolatile memory, a voltage of about 20V is applied to the semiconductor substrate
100
. With the state-of-the-art technology, writing to memory cells block by block and simultaneous erasing, which respectively take several &mgr;sec and several msec, are carried out to make writing and erasing faster.
As apparent from this, erasure takes longer time than writing. If the edge of each gate electrode is located on the semiconductor substrate
100
at an area equivalent to the cathode electrode in erase mode, an electric field concentrates on this area, causing the edge portion to have a higher current density than that of the flat surface as implied above referring to FIG.
2
C.
The higher the current density of the FN current becomes, the larger the trap is formed in the gate oxide film. This leads to a variation in threshold voltage even at the stage of fewer writing and erasing cycles.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor memory device having a gate structure which prevents an electric field from concentrating on the widthwise edge portion of gate electrodes in order to reduce charges produced in an oxide film by electric stress, and a method of fabricating the same.
This invention provides memory cells having transistors which are so designed to prevent an electric field from concentrating on the widthwise edge portion of gate electrodes in order to reduce charges produced in an oxide film by electric stress. This structure can permit an electric field to be uniformly distributed over the gate electrodes and can thus contribute to fabricating stable memory transistors whose threshold voltage (Vth) has a less variation.
To achieve the above object, according to the first aspect of this invention, there is provided a semiconductor memory device comprising a semiconductor substrate having a major surface; a device region formed on the major surface of the semiconductor substrate; a device isolation region, formed by burying an insulating film in a trench formed in the major surface of the semiconductor substrate,

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