Semiconductor memory device having memory cells requiring no...

Details Semiconductor memory device having memory cells requiring no... Semiconductor memory device having memory cells requiring no...

2002-09-20

2003-09-23

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C345S182000, C345S182000

Reexamination Certificate

active

06625056

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device for storing information in accordance with the presence or absence of charges in a capacitor constituting of a memory cell.
2. Description of the Background Art
In a DRAM (Dynamic Random Access Memory) as a representative one of semiconductor memory devices, a memory cell is formed of one transistor and one capacitor, and the structure of a memory cell itself is simple. Consequently, the DRAM is regarded as a device which is optimum to realize higher packing density and larger capacity of a semiconductor device and used in various electronic devices.
FIG. 9
is a circuit diagram showing the configuration of one of memory cells arranged in a matrix on a memory cell array in a DRAM.
Referring to
FIG. 9
, a memory cell
500
is provided with an N-channel MOS transistor
502
and a capacitor
504
. N-channel MOS transistor
502
is connected to a bit line
508
and capacitor
504
and has a gate connected to a word line
506
. One end, which is different from an end connected to N-channel MOS transistor
502
, of capacitor
504
is connected to a cell plate
510
.
N-channel MOS transistor
502
is driven by word line
506
which is activated only when data is written or read, and is turned on only when data is written or read and is turned off at the other times.
Capacitor
504
stores binary information “1” or “0” in accordance with whether charges are accumulated or not. A voltage corresponding to the binary information “1” or “0” is applied to capacitor
504
via N-channel MOS transistor
502
from bit line
508
, thereby charging or discharging capacitor
504
to write data.
Specifically, in the case of writing data “1”, bit line
508
is precharged to a power supply voltage Vcc, and word line
506
is activated, thereby turning on N-channel MOS transistor
502
. Power supply voltage Vcc is applied from bit line
508
to capacitor
504
via N-channel MOS transistor
502
, and charges are accumulated in capacitor
504
. The state where the charges are accumulated in capacitor
504
corresponds to data “1”.
In the case of writing data “0”, bit line
508
is precharged to a ground voltage GND and word line
506
is activated, thereby turning on N-channel MOS transistor
502
. Charges are discharged from capacitor
504
to bit line
508
via N-channel MOS transistor
502
. The state where charges are not accumulated in capacitor
504
corresponds to data “0”.
On the other hand, at the time of reading data, bit line
508
is previously precharged to a voltage Vcc/2 and word line
506
is activated, thereby turning on N-channel MOS transistor
502
, and bit line
508
and capacitor
504
are energized. It makes a very small voltage change according to a charge accumulating state of capacitor
504
appear on bit line
508
, and a not-illustrated sense amplifier amplifies the very small voltage change to voltage Vcc or ground voltage GND. The voltage level of bit line
508
corresponds to the state of read data.
Since the above-described data reading operation is destructive reading, word line
506
is activated again in a state where bit line
508
is amplified to voltage Vcc or ground voltage GND in accordance with the read data, and capacitor
504
is recharged by an operation similar to the above-described data writing operation. By the operation, data once destroyed by the data reading operation recovers to the original state.
In a memory cell in the DRAM, charges in capacitor
504
corresponding to stored data leak due to various causes and are gradually lost. That is, stored data decays with time. Consequently, in the DRAM, before a voltage change in bit line
508
corresponding to stored data becomes undetectable in the data reading operation, a refresh operation of reading the data once and rewriting the data is executed.
In the DRAM, all of memory cells have to always periodically be subjected to the refresh operations. This point is the drawback of the DRAM since it is disadvantageous to realize higher speed and lower power consumption. The DRAM is inferior to an SRAM (Static Random Access Memory) which does not require refresh operations from the viewpoint of high speed and low power consumption. The DRAM, however, has a simple structure of a memory cell and can be formed at high packing density as described above. Consequently, the cost per bit is much lower as compared with other memory devices, so that the DRAM is in the mainstream of present RAMs.
On the other hand, an SRAM as also one of typical semiconductor memory devices is an RAM which does not require refresh operations indispensable for a DRAM.
FIG. 10
is a circuit diagram showing the configuration of one of memory cells arranged in a matrix on a memory cell array in a 6-transistors SRAM.
Referring to
FIG. 10
, a memory cell
700
is provided with N-channel MOS transistors
702
to
708
, P-channel MOS transistors
710
and
712
, and storage nodes
714
and
716
.
Memory cell
700
has a configuration that a flip-flop obtained by cross-coupling an inverter formed of N-channel MOS transistor
702
and P-channel MOS transistor
710
and an inverter formed of N-channel MOS transistor
704
and P-channel MOS transistor
712
is connected to a pair of bit lines
718
and
720
via two N-channel MOS transistors
706
and
708
as transfer gates.
In memory cell
700
, states of voltage levels of storage nodes
714
and
716
correspond to stored data. For example, the state where storage nodes
714
and
716
are at the H and L levels, respectively, corresponds to stored data “1”, and the state where storage nodes
714
and
716
are at the L and H levels, respectively, corresponds to stored data “0”. Data on cross-coupled storage nodes
714
and
716
is in a bi-stable state which is maintained as long as a predetermined power supply voltage is supplied. With respect to this point, the SRAM is fundamentally different from a DRAM in which charges accumulated in the capacitor dissipate with time.
In memory cell
700
, in data writing operation, voltages at opposite levels corresponding to write data are applied to the pair of bit lines
718
and
720
, and word line
722
is activated to turn on transfer gates
706
and
708
, thereby setting the state of the flip flop. On the other hand, data reading operation is performed in such a manner that word line
722
is activated to turn on transfer gates
706
and
708
, potentials on storage nodes
714
and
716
are transmitted to bit lines
718
and
720
, and a voltage change in bit lines
718
and
720
at this time is detected.
Memory cell
700
is formed of six bulk transistors. There is also an SRAM having a memory cell which can be formed of four bulk transistors.
FIG. 11
is a circuit diagram showing the configuration of one of memory cells arranged in a matrix on a memory cell array in a 4-transistors SRAM.
Referring to
FIG. 11
, a memory cell
750
is provided with, in place of P-channel MOS transistors
710
and
712
in memory cell
700
, P-channel thin film transistors (hereinafter, referred to as “P-channel TFT”)
730
and
732
. As P-channel TFTs
730
and
732
, resistors of high resistance may be used. “4-transistors” in the name of the 4-transistors SRAM denotes that one memory cell has four bulk transistors. “Bulk” means that a transistor is formed in a silicon substrate in contrast to the meaning that a TFT is formed on a substrate. In the following, a transistor formed in a silicon substrate will be referred to as a “bulk transistor” in contrast to thin film devices such as TFT formed on a substrate.
Since the operation principle of memory cell
750
is basically the same as that of memory cell
700
, its description will not be repeated.
P-channel TFTs
730
and
732
are formed on upper layers of N-channel MOS transistors
702
and
704
, so that the 4-transistors SRAM has an advantage such that its cell area is made smaller than that of a 6-transistors SRAM. On the other ha

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