Static information storage and retrieval – Systems using particular element – Semiconductive
Reexamination Certificate
2001-10-19
2003-06-10
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Semiconductive
C365S168000
Reexamination Certificate
active
06577530
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor memory devices, and particularly to a technique useful for the application to what has highly-reliable and large storage-capacity semiconductor memory circuits.
The kinds of semiconductor memory devices can be broadly classified into RAM (random access memory), and ROM (read-only memory). Of these memories, dynamic RAM (DRAM) is used in largest quantities for main memory of computer. The memory cells of that memory are each formed of one storage electrostatic capacitor and a transistor that causes this capacitor to store electric charges and to read out the charges. This memory is suitable for large-scale integration because it can be formed of the smallest number of elements as a RAM. Therefore, it has been mass-produced at relatively low cost.
However, the DRAM has a drawback that the operation is easy to be unstable. The greatest factor for the instability is that the memory cell itself has no amplifying action, and hence the signal voltage read out from the memory cell is so small that the operation of the memory cell is easily affected by various kinds of noises. In addition, the information of charges stored in the capacitor disappears due p-n junction (leakage) current within the memory cell. Thus, before the information disappearence, the memory cell is required to refresh (writing for restoration), thereby holding the stored information. The period of this refreshment is called refreshment time, and under the present situation it is about 100 ms. However, it is necessary to increase the period with the increase of the storage capacity. In other words, the leakage current, which is required to be suppressed, becomes increasingly difficult to suppress as the memory device is further small-sized.
The memory that can solve this problem is ROM, particularly flash memory. The cell of the flash memory, as well known, is as small as the DRAM cell or smaller, and has a gain so that it can produce a substantially large signal voltage enough to stably operate. Moreover, since charges are stored at a storage node surrounded by an insulating film, there is no p-n junction current and hence the refreshing operation is not required unlike the DRAM. However, since a slight tunnel current is caused to flow at the storage node and store charges thereat, it takes an extremely long time to write. Repetition of writing will cause current to forcibly flow in the insulating film, thus gradually degrading the insulating film, so that finally the insulating film becomes a conductive film that cannot hold the stored charges. Therefore, the number of times that the flash memory produced as a commodity writes is generally limited to 100 thousands. In other words, the flash memory cannot be used as RAM. Since the DRAM and flash memory are both high-capacity memory, but each have advantages and disadvantages as described above, those different advantages must be used in order that the features of the memories can be well selected.
The so-called three-transistor cell that has a storage MOSFET for storing an information voltage at the gate, and a writing MOSFET for making the information voltage be written at the gate, is well known as described in, for example, “VLSI MEMORY” written by Kiyoo Ito, and published by Baifukan Nov. 5, 1994, pp. 12 to 15. In addition, JP-A-10-228781 (laid-open on Aug. 25, 1998) discloses a memory circuit having the three-transistor cell used for storing three or more logic states to thereby equivalently increase the storage capacity.
In the memory circuit proposed in the gazette, however, the gate voltage is amplified by the storage MOSFET, a selection MOSFET provided at the drain and a load resistor provided on a read data line, to be produced on the read data line. Therefore, since the variations themselves of the characteristics of the storage MOSFETs and selection MOSFETs of the memory cells appear in the output voltage, it is extremely difficult to stably read out voltages of three values or more, producing digital data. In addition, since the source and drain of the writing MOSFET are connected to the gate of the storage MOSFET, the multi-value information voltage is lost by the p-n junction (leakage) current like the DRAM. In order to securely hold this multi-value information voltage, it is necessary to make such refreshing operation as to read out the information voltage with a constant period, digitize it, convert to an analog voltage and again write in the original memory cell.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a semiconductor memory device that has achieved a high-reliability large-storage capacity.
It is another object of the invention to provide a semiconductor memory device that has improved the usability in addition to the high-reliability large-storage capacity.
The above objects, other objects and noble features of the invention will become apparent from the description of this specification and the accompanying drawings.
According to one aspect of the invention, there is provided a semiconductor memory device in which memory cells are used which each have a MOSFET that holds an information voltage of three or more values at its gate, a writing transistor that applies the information voltage of three or more values to the gate of the MOSFET, and a reading transistor connected in series with the MOSFET, the writing transistor is controlled in a switching manner by write word lines in accordance with an address signal, the reading transistor is controlled in a switching manner by read word lines in accordance with an address signal, the information voltage is applied to write bit lines that are arranged in the direction perpendicular to the write word lines, a memory current flowing through the MOSFET and the reading transistor is caused to flow in read bit lines that are arranged in the direction perpendicular to the read word lines, and a plurality of reference voltages corresponding to the information voltage of three or more values are applied from a common source line to the sources of the MOSFETs so that the information of three or more values can be read by a combination of on-state/off-state of the MOSFET and the plurality of reference voltages.
According to another aspect of the invention, there is provided a semiconductor memory device in which memory cells are used which each have a MOSFET that holds an information voltage of three or more values at its gate, a writing transistor that applies the information voltage of three or more values to the gate of the MOSFET, and a reading transistor connected in series with the MOSFET, the writing transistor is controlled in a switching manner by write word lines in accordance with an address signal, the reading transistor is controlled in a switching manner by read word lines in accordance with an address signal, the information voltage is applied to write bit lines that are arranged in the direction perpendicular to the write word lines, and the source voltages of the MOSFETs are produced on read bit lines arranged in the direction perpendicular to the read word lines, and converted into a digital signal.
REFERENCES:
patent: 4811305 (1989-03-01), Watanabe et al.
patent: 5737261 (1998-04-01), Taira
patent: 5796650 (1998-08-01), Wik et al.
patent: 5903505 (1999-05-01), Wik et al.
patent: A-10-228781 (1998-08-01), None
Japanese Literature “VLSI Memory” by Kiyoo Ito, Nov. 5, 1994, pp. 12-15.
Ito Yutaka
Muranaka Masaya
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