Semiconductor memory device having memory block configuration

Details Semiconductor memory device having memory block configuration Semiconductor memory device having memory block configuration

2011-08-16

2011-08-16

Phan, Trong (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230030, C365S230060, C365S226000, C365S185090, C365S185110, C365S185290

Reexamination Certificate

active

08000159

ABSTRACT:
A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the analog and logic circuits and the pad band including power supply and data pads. The analog circuit is positioned close to the power supply pad, so that voltage drop due to the resistance of power supply interconnection is restricted. It is also possible to separate a charge pumping power supply interconnection and a peripheral circuit power supply interconnection in the vicinity of the power supply pad.

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